United Microelectronics Corp.

United Semiconductor Corp.

Other

United Semiconductor Circuit Corp.

Chih-Ching Hsu

Shu-Jen Chen

Ching-Hsing Hsieh

Shuenn-Jeng Chen

Brian Wang

Jiunn-Hsien Lin

Chih-Hsiang Hsiao

William Lu

Ruoh-Haw Chang

Jacky Kuo

Hung-Yu Kou

Yung-Chieh Kuo

A method is provided for forming fluorosilicate glass (FSG) layers that serve as inter-metal dielectric (IMD) layers in a semiconductor wafer with a high moisture-resistant capability. In particular, the method can nonetheless allow the resultant semiconductor circuit to have a low RC delay. The method includes the step of subjecting the FSG layer to a plasma treatment so as to form a moisture-resistant layer over the FSG layer. In the plasma treatment, the ionized gas of ammonia is used as the plasma. As a result of this plasma treatment, a layer of nitrogen-containing compound having a high moisture-resistant property is formed over the FSG layer, which serves as a moisture-resistant layer that can protect the FSG layer from absorbing moistures.

Method of forming fluorosilicate glass (FSG) layers with moisture-resistant capability

A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Method for fabricating an interconnect

A method of planarizing a dielectric layer comprising the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the substrate. Next, a rapid thermal process is applied heating the borophosphosilicate layer to cause a thermal flow, and then the borophosphosilicate layer is etched back so that a planar surface is obtained. Finally, a passivation layer is formed over the borophosphosilicate glass layer to prevent the formation of pits in subsequent pre-metal wet etching operations.

Method of planarizing dielectric layer

An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the cured third dielectric layer. A chemical-mechanical polishing process is performed using the cured dielectric layer as a stop layer. A cap layer is formed on the fourth dielectric layer.

Method for forming inter-metal dielectrics

A method for manufacturing an even dielectric layer. A substrate having a patterned conductive layer formed thereon is provided. A first dielectric layer with a relatively high dopant dosage is formed on the substrate and the patterned conductive layer. A second dielectric layer with a relatively low dopant dosage is formed on the first dielectric layer. A chemical-mechanical polishing process is formed.

Method for manufacturing even dielectric layer

The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a first silicide layer is formed on polysilicon layer. The substrate is patterned and then, etched to form a gate structure. A spacer is formed on the sidewall of the gate structure and source/drain region is formed adjacent thereto. A metal layer is covered on the surface of the substrate. The substrate is performed a thermal process to convert the portion of the metal layer on gate structure and source/drain region into self-aligned silicide.

Method of fabricating self-aligned silicide

The invention relates to a method for manufacturing of a titanium self-aligned silicide (Salicide). This process includes of forming a metal layer over the surfaces of the semiconductor substrate and the gate electrode. Then, a rapid thermal process is performed with three stages to form the salicide, for example, titanium silicide, at the interface between the titanium and silicon, namely on the surfaces of the gate electrode and source/drain region. The rapid thermal process with three stages includes using the first stage with the first temperature to form the early titanium silicide having the C49 phase. The temperature is raised to a second temperature and the RTA process is performed with nitrogen gases to transform the high resistance phase C49 of the titanium nitride into a low resistance phase C54 in the second stage. Then, the temperature is rapidly raised to a third temperature to transform the C49 phase into the C54 phase completely and to prevent the agglomeration phenomenon.

Method of manufacturing self-aligned silicide

A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.

Method of forming a via with plasma treatment of SOG

The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Method to grow self-aligned silicon on a poly-gate, source and drain

A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and forming a salicide layer by thermally reacting the metal stack and the wafer followed by a chemical etching which removes the unreacted portions of the metal stack. The portions of the metal stack on Si can react with Si to form a TiSi.sub.2 layer, thus forming TiSi.sub.2 --TiN--TiSi.sub.2. The TiSi.sub.2 layer over the TiN layer acts as a mask in the chemical etching and protects the TiN layer from been etched. The diffusion barrier layer is thus formed simultaneously within the fabricating of salicide.

Growing community of inventors

Hsinchu, Taiwan

Chih-Ching Hsu