Taiwan Semiconductor Manufacturing Comp. Ltd.

Chih-Chang Cheng

Ruey-Hsin Liu

Fu-Chih Yang

Ru-Yi Su

Chun Lin Tsai

Fu-Yu Chu

Ker Hsiao Huo

Jen-Hao Yeh

Po-Chih Chen

Tung-Yang Lin

Ming-Ta Lei

Shih-Fen Huang

Chih-Wen Yao

Chun-Lin Tsai

Hsiao-Chin Tuan

Ker-Hsiao Huo

Kong-Beng Thei

Chih-Hsin Ko

Chien-Chih Chou

Kuang-Hsin Chen

Yi-Huan Chen

Chen-Liang Chu

Hsin-Chih Chiang

Ta-Yuan Kung

Eric Huang

Fu Chin Yang

Hsiao Chin Tuan

Chia-Chin Shen

Chien-Hung Liu

Chih-Wei Hung

Tsung-Hao Yeh

Hsin-Fu Lin

Shiang-Hung Huang

Chih-Wen (Albert) Yao

In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Layout to reduce noise in semiconductor devices

A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within

A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer.

Method of making triple well isolated diode

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Plate design to decrease noise in semiconductor devices

A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

Semiconductor device having multiple wells and method of making

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

High voltage resistor with high voltage junction termination

A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

Semiconductor isolation structure and method for making the semiconductor isolation structure

A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

Transistor device with a gate structure having recesses overlying an interface between isolation and device regions

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

Semiconductor structure having field plate and associated fabricating method

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Embedded JFETs for high voltage applications

A semiconductor device includes a substrate and a gate structure over a top surface of the substrate. The semiconductor device further includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well surrounds the source. The semiconductor device further includes a second well having a second dopant type opposite the first dopant type, wherein the second well surrounds the drain, an entirety of an upper most surface of the second well between the drain and the first well is coplanar with the top surface of the substrate, and the second well is spaced from the first well.

Semiconductor device having multiple wells

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Hsinchu, Taiwan

Chih-Chang Cheng