Qualcomm Incorporated

Conexant Systems, Inc.

Chiew-Guan Tan

Wilson Jianbo Chen

Reza Jalilizeinali

Sumit Rao

Lalan Jee Mishra

Brian Matthew Henderson

Richard Dominic Wietfeldt

Shiqun Gu

Jung Pill Kim

Vidhya Ramachandran

Taehyun Kim

Christopher Kong Yee Chun

Aliasgar Presswala

Eugene Robert Worley

Todd Robert Sutton

Helena Deirdre O'Shea

Wolfgang Roethig

Umesh Srikantiah

Gregory Ameriada Uvieghara

Gordon P Lee

Alex Kuang-Hsuan Tu

Mark R Tennyson

ZhenQi Chen

Gregory Lynch

Scott Davenport

Yeshwanth Kumar Mallavajula

Rohit Shetty

Gregory A Uvieghara

In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.

Dynamic gate-overdrive voltage boost receiver

An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.

Dynamic transistor gate overdrive for input/output (I/O) drivers and level shifters

An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.

Static and intermittent dynamic multi-bias core for dual pad voltage level shifter

Certain aspects of the present disclosure generally relate to a level-shifting circuit. The level-shifting circuit generally includes a first pull-up path having at least one first diode and at least one first transistor, and a second pull-up path having at least one second diode and at least one second transistor. The level-shifting circuit may also include a first pull-down path having a third transistor and a fourth transistor, wherein the fourth transistor is coupled between the third transistor and the first diode; a second pull-down path having a fifth transistor and a sixth transistor, wherein the sixth transistor is coupled between the fifth transistor and the second diode; and an overvoltage protection circuit coupled to gates of the fourth transistor and the sixth transistor.

Level shifter with auto voltage-bias reliability protection

Aspects generally relate to receivers, and in particular to a receiver that converts a high-voltage input signal into a low-voltage signal. The high voltage input signal is split into a upper portion and a lower portion. The upper portion is coupled to a high input receiver that is powered by dynamic supply shifters that can vary supply voltage during operation to optimize switching.

Dynamic power supply shifting

Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

Back power protection (BPP) in a system on a chip (SOC) with critical signaling scheme

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus

The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

Apparatus and method for data level shifting with boost assisted inputs for high speed and low voltage applications

System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

Single line PMIC-host low-level control interface

A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX&#x3e;CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

Latch-based power-on checker

An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

High voltage input receiver using low-voltage devices

An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (V) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while Vcontinues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when Vbegins transitioning from high to low logic voltages, and transitions back to the low bias voltage while Vcontinues to transition towards the low logic voltage.

Input/output (I/O) driver implementing dynamic gate biasing of buffer transistors

A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Output driver with back-powering prevention

A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Growing community of inventors

San Diego, CA, United States of America

Chiew-Guan Tan