National Yang Ming Chiao Tung University

Chien-Yu Hsieh

Pin Chia Su

Ching-Te Chuang

Ming-Long Fan

Pi-Ho Hu

Yin-Nien Chen

The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VFinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.

Independently-controlled-gate SRAM

The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.

Growing community of inventors

Hsinchu, Taiwan

Chien-Yu Hsieh