Siliconware Precision Industries Co., Ltd.

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Siliconware Precision Industries, Ltd.

Chien-Ping Huang

Cheng-Hsu Hsiao

Chun-Chi Ke

Chih-Ming Huang

Han-Ping Pu

Tzong-Da Ho

Chi-Chuan Wu

Fu-Di Tang

Yu-Po Wang

Ho-Yi Tsai

Pang-Chun Lin

Chun-Yuan Li

Tzong-Dar Her

Han-PIng Pu

Chih-Chin Liao

Randy H Y Lo

Chang-Yueh Chan

Eric Ko

Jui-Yu Chuang

Shih-Kuang Chiu

Chin-Huang Chang

Cheng-Yi Chang

Chin-Tsai Yao

Yueh-Ying Tsai

Lien-Chi Chan

Chien-Chih Chen

Chang-Fu Lin

Jung-Pin Huang

Yun-Lung Tsai

Jui-Hsiang Hung

Ying-Ren Lin

Lian-Cherng Chiang

Yu-Chieh Tsai

Fang-Lin Tsai

Chiang-Cheng Chang

Yih-Jenn Jiang

Cheng-Chia Chiang

Chung-Lun Liu

Chien-Te Chen

Chun-An Huang

Jui-Meng Jao

Chin-Teng Hsu

Cheng-Yuan Lai

Kevin Chiang

Kevin Yu

Holman Chen

Hsiao-Jen Hung

Yung-Kang Chu

Min-Shun Hung

Chen-Hsu Hsiao

Che-Jung Chang

Grace Yang

Wei-Chen Tseng

Kook-Jui Tai

Chin-Yuan Hong

Michael Chang

Hsin-Yi Liao

Ming-Chih Hsieh

Hsi-Chang Hsu

Yu-Ting Lai

Ke-Chuan Yang

Wen-Tsung Tseng

Jeng-Yuan Lai

Chin-Te Chen

Wen-Ta Tsai

Chin-Yuan Hung

Chang-Fu Chen

Tzu-Yi Tien

Cheng-Shiu Hsiao

April Chen

Wen Cheng Lee

Ming-Chun Laio

Nan-Jang Chen

Yo-Yi Tsai

Cha-Yun Yin

Yvonne Lee

Tse-Wen Chang

Wei-Chun Lin

Jung-Ping Huang

Lien-Chih Chan

Keng-Yuan Liao

Yuan-Chun Li

Jenn-Shyh Yu

Chien Yuan Tsui

Niang Yi Cheng

Chun-Ming Liao

Chiao-Yi Lee

Chia-Yu Hung

Raymond J M Jao

Chung-Chi Lin

A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

Method for fabricating carrier-free semiconductor package

Carrier-free semiconductor package and fabrication method

An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

Method for fabricating EMI shielding package structure

A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

Fabrication method of semiconductor package without chip carrier

A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

Method for fabricating quad flat non-leaded package structure with electromagnetic interference shielding function

A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Fabrication method of semiconductor package having electrical connecting structures

A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.

Chip scale package with electronic component received in encapsulant, and fabrication method thereof

A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

Semiconductor package structure

Semiconductor package without chip carrier and fabrication method thereof

EMI shielding package structure and method for fabricating the same

A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

Package structure

A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Fabrication method of semiconductor package device, and fabrication method of semiconductor package structure

Quad flat non-leaded package structure with electromagnetic interference shielding function and method for fabricating the same

Semiconductor package having electrical connecting structures and fabrication method thereof

A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization.

Package having MEMS element and fabrication method thereof

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Taichung, Taiwan

Chien-Ping Huang