Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Ming Chiu

Chen-Hua Douglas Yu

Wen-Chih Chiou

Tsang-Jiuh Wu

Shin-Puu Jeng

Jing-Cheng Lin

Shau-Lin Shue

Weng-Jin Wu

Hung-Pin Chang

Fang Wen Tsai

Chen-Yu Tsai

Chia-Ho Chen

Shih-Hui Wang

Chia-Hao Hsu

Yung-Chi Lin

A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer. The first bonding dielectric layer separates the second bonding dielectric layer from the dielectric material layer, and the first die and the second die are bonded through bonding the second bonding dielectric layer with the first bonding dielectric layer and bonding the conductive feature with the TSV.

Die stack structure and method of fabricating the same

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Alignment mark and method of formation

A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Multi-layer interconnect structure for stacked dies

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Hsin-Chu, Taiwan

Chien-Ming Chiu