Taiwan Semiconductor Manufacturing Comp. Ltd.

Acer Inc.

Industrial Technology Research Institute

Voltafield Technology Corporation

Winbond Electronics Corporation

Promos Technologies, Inc

Nan Ya Technology Corporation

Other

National Tsing Hua Universitiy

Powerchip Semiconductor Corporation

Chien-Min Lee

Shy-Jay Lin

Li-Chung Lo

Chung-Te Lin

Tai-Yen Peng

Xinyu Bao

Han-Ting Tsai

Pin-Ren Dai

Hui-Hsien Wei

Wei-Chih Wen

Chia-Wen Hsieh

Tung-Ying Lee

Wei-Chen Pao

Cheng-Hsien Wu

Mingyuan Song

Hengyuan Lee

Sheng-Chih Lai

Yen-Lin Huang

Jen-Hsien Chen

Ming-Yuan Song

Fu-Tai Liou

Jyu-Horng Shieh

Tzu-Ming Lin

Wei-Su Chen

Yi-Chan Chen

Hong-Hui Hsu

William Joseph Gallagher

Min-Hung Lee

Wen-Han Wang

Yen Chuo

Te-Sheng Chao

Elia Ambrosi

Ying-Yu Chen

Kuang-Ching Chen

Ren-Jr Chen

Nai-Chung Fu

Chia-Pang Yen

Tsung-Hua Tsai

Chia-Han Lee

Keng-Te Liao

Chung-Ju Lee

Tung Ying Lee

Wei-Hao Liao

Hsi-Wen Tien

Chih-Wei Lu

Yu-Sheng Chen

Ji-Feng Ying

Yu-Teng Dai

Tsann Lin

Jung-Mao Lin

Hiroki Noguchi

Chen-Feng Hsu

Ming-Jinn Tsai

William J Gallagher

Chih-Chien Liang

Chin-Fu Kao

Ming-Sheng Yang

Kai-Tai Chang

Chung-Lien Ho

Nuo Xu

Chang-Lung Hsiao

Tsung-Shune Chin

Wern-Ho Sheen

Cheng-Chun Chang

Ta-Yung Wong

Jia-Mou Lee

Yu-Fang Chiu

Der-Sheng Chao

Tai-Lang Tang

Chih Wei Chen

Chao-Chung Huang

Kuan-Hao Chen

Chia-Chin Tsai

Chi-Feng Pai

Cheng-Wei Peng

Chen-Yu Hu

A magnetic memory device includes a substrate, a spin-orbit torque (SOT) induction structure, and a magnetic tunnel junction (MTJ) stack. The SOT induction structure is disposed over the substrate. The SOT induction structure includes a metal and at least one dopant. The MTJ stack is disposed over the SOT induction structure.

Magnetic memory device and manufacturing method thereof

A memory device and a method of manufacturing the same are provided. The memory device includes a semiconductor substrate, an interconnect structure and a memory cell. The interconnect structure is disposed over the semiconductor substrate, and the memory cell is disposed over the interconnect structure and electrically coupled with the semiconductor substrate and the interconnect structure. The memory cell includes a spin Hall electrode layer, an MTJ pillar, a hard mask, and a spacer. The MTJ pillar is disposed on the spin Hall electrode layer, the hard mask is disposed on the MTJ pillar, and the spacer is disposed on sidewalls of the MTJ pillar and the hard mask. Suitably, the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion.

Memory cell, memory device and manufacturing method thereof

Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.

Semiconductor device and manufacturing method of semiconductor device

A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Memory device

An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Memory device and manufacturing method thereof

First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

First fire operation for ovonic threshold switch selector

A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Magnetic tunneling junction with synthetic free layer for SOT-MRAM

A communication device for handling a reference signal (RS) reporting includes at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving at least one reference signal (RS) from a network; performing at least one measurement according to the at least one RS, to generate at least one measurement result; selecting an RS from the at least one RS according to the at least one measurement result; and determining whether to report the RS to the network.

Device and method for handling a reference signal reporting

A communication device for handling physical uplink (UL) shared channel (PUSCH) transmissions, comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of receiving an indicator indicating a plurality of physical uplink (UL) shared channel (PUSCH) repetitions from a network; determining at least one nominal transmission duration for the plurality of PUSCH repetitions; and transmitting the plurality of PUSCH repetitions to the network in the at least one nominal transmission duration according to the indication.

Device of handling PUSCH transmissions

Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Methods of writing and forming memory device

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

SOT-MRAM with shared selector

A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Semiconductor device and method for forming the same

A communication device for handling a hybrid automatic repeat request (HARQ) transmission, comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device, wherein the at least one storage device stores instructions, and the at least one processing circuit is configured to execute the instructions of: receiving a configuration from a network, wherein the configuration comprises a time domain resource allocation (TDRA) table and a set of a plurality of timing values; and receiving a downlink (DL) control information (DCI) from the network, wherein the DCI indicates a row of the TDRA table for at least one physical DL shared channel (PDSCH) reception and indicates a timing value of the set of the plurality of timing values for the HARQ transmission corresponding to the at least one PDSCH reception.

Device and method for handling a hybrid automatic repeat request transmission

A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Memory devices and methods of forming the same

A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Memory device and method of fabricating the same

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Taipei, Taiwan

Chien-Min Lee