Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Chien Ling Hwang

Chung-Shi Liu

Chen-Hua Douglas Yu

Yeong-Jyh Lin

Bor-Ping Jang

Yi-Wen Wu

Yi-Li Hsiao

Hsin-Hung Liao

Ying-Jui Huang

Cheng-Chung Lin

Hsiao-Chung Liang

Mirng-Ji Lii

Ming-Che Ho

Ming-Da Cheng

Pei-Hsuan Lee

Hung-Jui Kuo

Hao-Yi Tsai

Chih-Wei Lin

Tin-Hao Kuo

Jui-Pin Hung

Yung-Chi Lin

Yu-Chia Lai

Chia-Lin Yu

Hung-Pin Chang

Shu-Rong Chun

Lin-Wei Wang

Ching-Hua Hsieh

Tsung-Ding Wang

Meng-Tse Chen

Hsin-Yu Pan

Jung Wei Cheng

Kuo Lung Pan

Zheng-Yi Lim

Chen-Shien Chen

Ching-Wen Hsiao

Chun-Chieh Wang

Hui-Jung Tsai

Po-Yuan Teng

Yen-Chang Hu

An-Jhih Su

Han-Ping Pu

Wen-Hsiung Lu

Chih-Hang Tung

Tung-Liang Shao

Kim Hong Chen

Yu-Liang Lin

Meng-Wei Chou

Tsai-Tsung Tsai

Su-Chun Yang

De-Yuan Lu

Yu-Ting Chiu

Kuo Cheng Lin

Kuei-Wei Huang

Hui-Min Huang

Chih-Fan Huang

Kuo-Lung Pan

Jean Wang

Yi-Yang Lei

Fu-Kang Tien

Jen-Chun Liao

Cheng Hsun Chan

Jyh-Chemg Sheu

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

Bonding with pre-deoxide process and apparatus for performing the same

A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

Aligning bumps in fan-out packaging process

In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

Integrated circuit package and method

In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.

Integrated circuit packages having support rings

A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

Anisotropic carrier for high aspect ratio fanout

Method of forming integrated circuit packages with mechanical braces

A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Via structure for packaging and a method of forming

A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.

Wafer level transfer molding and apparatus for performing the same

An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same

A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

Fan-out interconnect structure and method for forming same

A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.

Wafer-level underfill and over-molding

Growing community of inventors

Hsinchu, Taiwan

Chien Ling Hwang