United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Micron Electronics, Inc.

Victory Gain Group Corporation

Chien-Li Kuo

Sun-Chieh Chien

Yung-Chang Lin

Po-Tao Chu

Shen-Ping Wang

Kun-Ming Huang

Ming-Tse Lin

Hsin-Chih Lin

Kuei-Sheng Wu

Ming-Hong Chang

Tzung-Han Lee

Lieh-Chuan Chen

Ching-Li Yang

Wei-Wu Liao

Jui-Meng Jao

Jheng-Sheng You

Chun-Yi Yang

Felix Ying-Kit Tsui

Hsin-Li Cheng

Chun-Hung Chen

Chu-Fu Lin

Jyun-Ying Lin

Chun-Liang Hou

Kai-Kuang Ho

Hui-Ling Chen

Clark Lee

Ping-Chang Wu

Jing-Hwang Yang

Chung-Lei Chen

Wen-Sheng Wang

Chen-Shien Chen

Chin-Fu Kao

Kuo-Chio Liu

Chien-Chen Li

Po-Wei Chen

Chung-Cheng Chen

Chia-Fang Lin

Yun-San Huang

Shih-Hsiang Tai

Min-Chin Hsieh

Kuen-Shian Chen

Scott Liu

Chuan-Hsien Fu

Chien-Hung Chen

Li-Hsien Huang

Pei-Haw Tsao

Chi-Mao Hsu

Yao-Chun Chuang

Wen-Jung Liao

Benjamin Szu-Min Lin

Tsun-Min Cheng

Shu-Ru Wang

Wen-Yi Lin

Chi-Fa Ku

Tung-Hsing Lee

Ting-Ting Kuo

Tsai-Yu Wen

Kuang-Chun Lee

Jun He

Bing-Chang Wu

Yu-Han Tsai

Jung-Chao Chiou

Chih-Yuan Chan

Yu-Lin Wang

Kuo-Ming Chen

Andy Chuang

Szu-Hao Lai

Ruey-Chyr Lee

Chuen-Huei Yang

Chih-Ming Su

Huei-Ru Tsai

San-Fu Lin

Chun-Wei Kang

Chi-Fu Lin

Chung-Sung Chiang

Army Chung

Jia-Jia Chen

Ching-Wei Hsu

Chia-Chun Sun

Shuen-Cheng Lei

Cheng-Hsin Chen

Fu-Chao Liu

Jui-Hung Cheng

Jing-hwang Yang

Jiun-Hau Liao

Chien-Hsien Chen

Buo-Chin Hsu

Cheng-Pu Chiu

Ming-I Hsu

In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

Dummy through vias for integrated circuit packages and methods of forming the same

A method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component including: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate including bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

Method of forming integrated circuit packages by bonding package component having first carrier to package substrate having second carrier

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Passivation scheme for pad openings and trenches

Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

Heat dissipating features for laser drilling process

An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Image sensor and manufacturing method thereof

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Low warpage high density trench capacitor

A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Semiconductor device package having metal thermal interface material

A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Semiconductor arrangement and method of making

A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Semiconductor device

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM.

Semiconductor device package having metal thermal interface material and method for forming the same

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Hsinchu, Taiwan

Chien-Li Kuo