Nan Ya Technology Corporation

Chien-Jung Yang

Chih-Huang Wu

Shian-Jyh Lin

Chien-Chang Huang

Neng-Tai Shih

Sheng-Tsung Chen

Yi-Jung Chen

A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.

DRAM fabrication method using oxidation spacers on pillar dielectric sidewalls

A method for forming a semiconductor device is provided. The method includes providing a substrate having a plurality of protrusions projecting from the substrate; forming a silicon layer over the substrate and each protrusion; performing an anisotropic etching to transfer the silicon layer into a silicon spacer positioned on a side wall of each protrusion; forming an oxide layer over the silicon spacer; and etching the substrate to form a recess on the substrate by using the oxide layer as a mask.

Semiconductor devices having recessed structures and methods of forming the same

A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

Growing community of inventors

Taoyuan County, Taiwan

Chien-Jung Yang