Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Hsun Chen

Jiun Yi Wu

Chung-Shi Liu

Chen-Hua Douglas Yu

Chien-Hsun Lee

Shou-Yi Wang

Jiun-Yi Wu

Yu-Ling Tsai

Chuei-Tang Wang

Chung-Hao Tsai

Wei-Ting Chen

Shih-Ya Huang

Ru-Gun Liu

Chih-Ming Lai

Kai-Chiang Wu

Tsung-Ding Wang

Wen-Chun Huang

Yu-min Liang

Boren Luo

Hao-Yi Tsai

Ching-Hua Hsieh

Yu-Hsiang Hu

Shih-Ming Chang

Jeng-Horng Chen

Shy-Jay Lin

Wei-Chih Chen

Ming Hung Tseng

Hsin-Yu Pan

Yen-Ping Wang

Tsung-Hsien Chiang

Tzu-Sung Huang

Hao-Cheng Hou

Jung-Wei Cheng

Chao-Hsien Huang

Ban-Li Wu

Ping-Chieh Wu

Yi-Che Chiang

Wei-Kang Hsieh

Tuan-Yu Hung

Wei-Long Wang

Faruk Krecinic

Ping Chieh Wu

Tuane Ying Fang

Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.

Semiconductor package and manufacturing method thereof

A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

Method for manufacturing semiconductor package with connection structures including via groups

A laminated structure and the manufacturing methods thereof are provided. The structure includes an interconnect substrate having a first surface and a second surface opposite to the first surface, an insulating encapsulant laterally wrapping the interconnect substrate, and a redistribution structure disposed on the first surface of the interconnect substrate and electrically connected with the interconnect substrate. The redistribution structure has a third surface facing the first surface and a fourth surface opposite to the third surface. The redistribution structure includes first pads, second pads located beside the first pads, and protective patterns disposed on the first pads and covering the first pads. The first pads include pad portions protruded from the fourth surface and the protective patterns are in contact with sidewalls and top surfaces of the pad portions of the first pads.

Laminated structure with pads and manufacturing method thereof

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Integrated circuit package and method

A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

Package structure, RDL structure comprising redistribution layer having ground plates and signal lines

A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

Semiconductor device and method of manufacture

A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

Semiconductor devices and methods of manufacturing

In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

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Zhutian, Taiwan

Chien-Hsun Chen