United Microelectronics Corp.

Chien-Hsing Lee

Shyh-Fann Ting

Cheng-Tung Huang

Tzyy-Ming Cheng

Tung-Hsing Lee

Sheng-Hao Lin

Min-Yi Chang

Da-Ching Chiou

Sun-Chin Wei

A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.

Testkey design pattern for gate oxide

A method for fabricating a flash memory device is described. A plurality of gates structures are formed on a substrate and each gate structure has a gate oxide layer. A floating gate is formed on the gate oxide layer. A cap layer is formed on the floating gate, and a spacer is formed on the sidewalls of the cap layer, the floating gate and the gate oxide layer. Thereafter, a trench is formed in every other space between the gate structures. A source region is formed on one side of the gate structure at the bottom of the trench in the substrate. Concurrently, a drain region is formed on another side of the gate structure in the substrate. After this, the cap layer and the spacer are removed, followed by forming a conformal dielectric layer on the substrate. A conductive layer is further formed on the substrate.

Fabrication method for a flash memory device

A flash memory device is described. A gate oxide layer is situated on a substrate next to a trench and a floating gate is located on the gate oxide layer. A source region is located in the substrate at the bottom of the trench and a drain region is located on a side of the floating gate. A dielectric layer is on the floating gate, the gate oxide layer and the trench. A control gate is located on the dielectric layer.

Structure of a flash memory device

A semiconductor wafer includes a silicon substrate, at least two floating gates positioned on the silicon substrate and a silicon nitride layer positioned on the surface of each floating gate. The method first uses a lithographic process and an ion implantation process to form a drain in the silicon substrate between the two floating gates. A passivation layer is then formed uniformly on the surface of the silicon substrate and the top surface and the sides of the floating gate. An etching process is performed later to form a spacer around each floating gate, the spacers between the floating gate are joined and cover the drain. Finally, an ion implantation process is performed, using the spacers as a hard mask, to form a source in the silicon substrate.

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Taipei County, Taiwan

Chien-Hsing Lee