United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Chien-Hao Chen

Chi-Mao Hsu

Hsin-Fu Huang

Min-Chuan Tsai

Wei-Yu Chen

Chin-Fu Lin

Chi-Yuan Sun

Chia-Lin Hsu

Tsun-Min Cheng

Chin-I Liao

Chia-Hung Wang

Sho-Shen Lee

Yung-Lun Hsieh

Bo-Syuan Lee

En-Chiuan Liou

Chun-Chi Yu

Ming-Yen Li

Ya-Hsueh Hsieh

Yu-Ping Wang

Jyh-Shyang Jenq

Yu-Hsiang Lin

Nien-Ting Ho

Hsuan-Hsu Chen

Yi-Ting Chen

Yi-Han Ye

Chang-Mao Wang

Tang-Chun Weng

Min-Hsien Chen

Hsin-Huei Wu

Chien-Wei Huang

Jing-Gang Li

Jian-Hong Su

Jhao-Hao Lee

Yu-Cheng Tung

Feng-Yi Chang

Fu-Che Lee

Chia-Chang Hsu

Yuan-Chi Pai

Kuei-Chun Hung

Yi-Wang Zhan

Kuan-Ying Lai

Chia-Ching Lin

Min-Chung Cheng

Wen-Liang Huang

Chia-Liang Liao

Yu-Wei Cheng

Hsin-Yu Hsieh

Kuo-Chun Huang

Feng-Lun Wu

Chung-Ping Hsia

Wei-Jhe Tzai

Min-Ying Hsu

En-Ting Liu

Hsin-Wei Lin

Der-Yu Chou

Yi Jing Wang

Chih-Yu Chiang

A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Method for correcting critical dimension measurements of lithographic tool

The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Patterning method and overlay measurement method

An alignment system includes a light source for emitting a light. An alignment mark is disposed on a substrate for receiving the light. The alignment mark includes a first pattern and a second pattern disposed on the substrate. The first pattern includes a first region and a second region. The second pattern includes a third region and a fourth region. The first region and the third region are symmetrical with respective to a symmetrical axis. The second region and the fourth region are symmetrical with respective to the symmetrical axis. The first region includes first mark lines parallel to each other. The second region includes second mark lines parallel to each other. A first pitch is disposed between the first mark lines adjacent to each other. A second pitch is disposed between the second mark lines adjacent to each other. The first pitch is different from the second pitch.

Alignment system and alignment mark

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

Manufacturing method for semiconductor pattern

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Method of forming layout of semiconductor device

A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

Semiconductor structure

The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.

Method for manufacturing semiconductor device

A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Manufacturing method of metal gate structure

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

Method of fabricating semiconductor device

A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Semiconductor structure and manufacturing method for the same

Semiconductor device

A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.

Structure of metal gate structure and manufacturing method of the same

Growing community of inventors

Yun-Lin County, Taiwan

Chien-Hao Chen