Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chien-Hao Chen

Tze-Liang Lee

Shih-Chang Chen

De-Wei Yu

Hsien-Ming Lee

Hung-Chin Chung

Chung-Chiang Wu

Ryan Chia-Jen Chen

Kuo-Tai Huang

Chia-Ching Lee

Chia-Lin Chen

Yi-Hsing Chen

Pin-Ju Liang

Chi On Chui

Yih-Ann Lin

Donald Y Chao

Ziwei Fang

Chun-Feng Nieh

Jr Jung Lin

Huan-Just Lin

Cheng-Lung Hung

Chi-Chun Chen

Yi-Shien Mor

Mo-Chiun Yu

Yong-Tian Hou

Pin-Hsuan Yeh

Huicheng Chang

Chih-Wei Chang

Li-Ting Wang

Su-Hao Liu

Liang-Gi Yao

Yan-Ming Tsai

Ju-Wang Hsu

Vincent Chang

Ming-Fang Wang

Keh-Chiang Ku

Chung-Ting Wei

Chao-Cheng Chen

Da-Yuan Lee

Kuo-Feng Yu

Chih-Tang Peng

Kuo-Bin Huang

Sheng-Liang Pan

Jian-Hao Chen

Chia-Wei Chen

Shih-Hang Chiu

Matt Yeh

Wei-Chin Lee

Shun Wu Lin

Shao-Jyun Wu

Hsin-Han Tsai

Chih-Yu Hsu

Tsung-Ta Tang

Yee-Chia Yeo

Chii-Horng Li

Yung-Cheng Lu

Harry Chuang

Pang-Yen Tsai

Ching-Hwanq Su

Jr-Jung Lin

Chun-Hung Lee

Jin-Aun Ng

Chien-Liang Chen

Hao-Ming Lien

Li-Ping Huang

Jun-Lin Yeh

Kang-Cheng Lin

Yuan-Shun Chao

Jei Ming Chen

Yi-Cheng Li

Yen-Ming Chen

Mong-Song Liang

Li-Zhen Yu

Dian-Hau Chen

Chia-Jen Chen

Hsiang-Ku Shen

Jr-Hung Li

Ming-Huan Tsai

De-Fang Chen

Yu Chao Lin

Yu-Chao Lin

Chi-On Chui

Yu-Chang Lin

Ying-Liang Chuang

Peng-Soon Lim

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Peng-Fu Hsu

Hung-Yi Huang

Min-Hsiu Hung

Yen-Chun Huang

Cheng-Po Chau

Yi-Ting Wang

Chien-Hao Huang

Mong Song Liang

Yi-Chun Huang

Ching-Lun Lai

Yun Chen Teng

Chia-Lin Chuang

A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.

Metal gate structure and method of forming the same

A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Semiconductor device with a work function layer having an oxygen-blocking dopant layer

A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Semiconductor device and method of manufacture

An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Semiconductor device and method

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Method of performing gap filling including filling trenches between dummy gate stacks on semiconductor fins/strips with semiconductor material

A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Selective hybrid capping layer for metal gates of transistors

Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Method of tuning threshold voltages of transistors

A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Gate resistance reduction through low-resistivity conductive layer

A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and an N-containing barrier layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first high-k gate dielectric layer and the second high-k gate dielectric layer include a same metal material. The first high-k gate dielectric layer has a first metal concentration, the second high-k gate dielectric layer has a second metal concentration, and the first metal concentration is less than the second metal concentration.

Semiconductor structure and method for forming the same

A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.

Semiconductor device and fabrication method therefor

A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first intervening layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first work function metal layer and the second work function metal layer include a same material. A thickness of the first work function metal layer is less than a thickness of the second work function metal layer.

Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending

Growing community of inventors

Chuangwei Township, Taiwan

Chien-Hao Chen