Intel Corporation

Chieh-jen Ku

Van H Le

Abhishek A Sharma

Bernhard Sell

Travis W LaJoie

Jack T Kavalieros

Tahir Ghani

Noriyuki Sato

Hui Jae Yoo

Fatih Hamzaoglu

Elliot Tan

Pei-Hua Wang

Juan G Alzate-Vinasco

Sarah Atanasov

Umut Arslan

Thoe Michaelos

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Two transistor memory cell using stacked thin-film transistors

Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Transistors, memory cells, and arrangements thereof

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Portland, OR, United States of America

Chieh-jen Ku