Taiwan Semiconductor Manufacturing Comp. Ltd.

Chie-Ming Yang

Cheng-Yeh Shih

Liang Szuma

Jih-Hwa Wang

Jun-Yang Lai

Chien-Jiun Wang

Hui-Chi Lin

Ming-Yu Chuang

Jiann-Liang Liou

Ko-Pin Lee

Allen Liao

Yen-Yi Lin

Shih-Wen Tu

Tzu-Yu Chang

Bou Fun Chen

Jih-Wha Wang

A method for managing a plurality of fabrication facilities comprises the steps of: identifying a proposed new or modified fabrication method, evaluating the fabrication method against decision criteria based on use of the fabrication method to fabricate a first product at a first one of the fabrication facilities, verifying the fabrication method against the decision criteria, based on using the fabrication method to fabricate a second product at a second one of the fabrication facilities, and adopting the fabrication method as a best known method among the plurality of fabrication facilities, if the fabrication method satisfies the decision criteria.

Method for implementing an engineering change across fab facilities

A new method is provided for treating the surface of a layer of passivation where this layer of passivation comprises silicon dioxide or silicon nitride. An oxygen rich layer is created over the surface of the layer of passivation. Under the first embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of plasma enhanced silicon nitride is deposited over the surface of the layer of silicon oxide, and a layer of oxynitride is deposited over the surface of the layer of plasma enhanced silicon nitride. Under the second embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of silicon nitride is deposited over the surface of layer of silicon oxide. The surface of the layer of silicon nitride is oxidized by N O or O plasma treatment.

Method to improve adhesion of molding compound by providing an oxygen rich film over the top surface of a passivation layer

A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.

Thermal annealing for preventing polycide void

A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. Silicon ions are implanted into the silicide layer. A hard mask layer is deposited over the silicide layer. Because of the presence of the silicon ions in the silicide layer, silicon atoms from the polysilicon layer do not diffuse into the silicide layer causing voids to form in the polysilicon layer. Therefore, the formation of silicon pits in the semiconductor substrate is prevented. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.

Ion implantation for preventing polycide void

Growing community of inventors

Hsin-Chu, Taiwan

Chie-Ming Yang