Taiwan Semiconductor Manufacturing Comp. Ltd.

Chie-Chieh Lin

Kuei-Shun Chen

Chia-Chu Liu

Chung-Ming Wang

Yu-Lun Liu

A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.

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Hsin-Chu, Taiwan

Chie-Chieh Lin