Texas Instruments Corporation

Chidi P R Chidambaram

Amitabh Jain

Douglas Ticknor Grider

Donald S Miles

An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide and/or cap oxide from the PMOS gate areas before doing PMOS implanting steps(K and M). The capping of the wafer (step G)with the cap oxide after the NMOS implant also prevents the arsenic from out diffusing from the silicon. Further embodiments include implanting directly on the base.

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Richardson, TX, United States of America

Chidi P R Chidambaram