Taiwan Semiconductor Manufacturing Comp. Ltd.

Chiarn-Lung Lee

Han-Chung Chen

Je Wang

Wei-Kun Yeh

Ying-Tzu Yen

Wei-kun Yeh

Huai-Jen Shu

Shyh-Jen Guo

Jun-Kai Peng

Yuan-Shing Jing

In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Method for etching passivation layer of wafer

A method for forming BPSG layers over PECVD silicon oxide layers by atmospheric chemical vapor deposition using ozone and TEOS is described. The method prevents the formation of voids in deep depressions such as are found between metallization lines or closely spaced polysilicon structures in flash memory integrated circuits. The method deposits the BPSG layer at ozone/TEOS flow rate ratio of 12:1 or greater. The voids are caused by excessive shrinkage of the BPSG which produces high stresses in the depressions during planarization reflow causing the BPSG to become detached from the underlying silicon oxide. The voids are measured as line defects in a double polysilicon flash memory circuit. The high ozone/TEOS ratio increases the density of the as-deposited BPSG layer which in turn produces reduced shrinkage of the layer during the subsequent planarization reflow. A correlation is found between BPSG shrinkage and line yield.

Method for preventing delamination of APCVD BPSG films

A method to store wafers, immediately after the deposition of a layer of BPSG, into an environment of dry air or dry N,or dry Ar or a N,O plasma chamber. This storage can occur over a variable period of time and with a variable delay between BPSG deposition and BPSG flow, dependent on which storage environment is applied. The surface of the deposited layer of BPSG is, in doing so, not exposed to H,O and the formation of unstable irregularities on the surface of the deposited BPSG is prevented.

Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition

A method for forming upon a microelectronics layer upon a substrate employed within a microelectronics fabrication a silicon oxide dielectric layer with enhanced density and reduced mobile species, ionic concentration and ionic mobility. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a blanket undoped silicon oxide glass dielectric layer employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) from tetra-ethyl-ortho-silicate (TEOS) vapor, wherein a high flow rate ratio of ozone gas to TEOS vapor affords enhanced density and reduced mobile species, ionic concentration and ionic mobility in the blanket silicon oxide glass dielectric layer. There is then formed a blanket boron-phosphorus doped silicon containing glass dielectric layer over the substrate employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) to complete the dielectric layer. The blanket undoped silicon oxide glass dielectric layer serves as a barrier to diffusion of mobile species from the doped silicon containing glass dielectric layer or other dielectric layers to attenuate hot carrier injection effects, which reduces degradation of device reliability.

Formation of dielectric layer employing high

A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.

Via structure using a composite dielectric layer

A method for removing a metal-fluoropolymer residue from an integrated circuit structure within an integrated circuit. There is first provided an integrated circuit having formed therein a metal-fluoropolymer residue. The metal-fluoropolymer residue is formed from a first plasma etch method employing a fluorocarbon containing etchant gas composition within the presence of a conductor metal layer within the integrated circuit. The metal-fluoropolymer residue is then exposed to a second plasma etch method employing a chlorine containing etchant gas composition to form from the metal-fluoropolymer residue a chlorine containing plasma treated metal-fluoropolymer residue. Finally, the chlorine containing plasma treated metal-fluoropolymer residue is removed from the integrated circuit through a stripping method sequentially employing an aqueous acid solution followed by an organic solvent.

Growing community of inventors

Hsin-chu, Taiwan

Chiarn-Lung Lee