Diodes Inc.

Mosel Vitelic Corporation

Industrial Technology Research Institute

Au Optronics Corporation

Chiao-Shun Chuang

Mao-Song Tseng

Chien-Ping Chang

Hsin-Huang Hsieh

Ching-Wen Wang

Yun-Pu Ku

Cheng-Chin Huang

Ming-Wei Tsai

Jie Li

Ke-Horng Chen

Cheng-Tsung Ni

Ta-Chuan Kuo

Tsung-Wei Pai

Su-Wen Chang

Kai-Yu Chen

Chien-Chung Hung

Han-Ping D Shieh

Chwan-Ying Lee

Cheng-Tyng Yen

Young-Shying Chen

Duane Wilcoxen

Fang-Chung Chen

TaChuan Kuo

Will Zhang

Tony Huang

Rain Liu

Hsing-Huang Hsieh

Thomas Tsai

A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

Vertical power semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.

Semiconductor structure and manufacturing method thereof

Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.

Semiconductor structures and manufacturing methods thereof

A semiconductor structure includes a silicon carbide layer, which has a unit region and a termination region surrounding the unit region. A first guard ring structure is located in the termination region of the silicon carbide layer, and adjoins a top surface of the silicon carbide layer. The first guard ring structure may include at least one first guard ring well region. A second guard ring structure is located in the silicon carbide layer and below the first guard ring structure. The second guard ring structure may include at least one second guard ring well region, which corresponds to the at least one first guard ring well region in a vertical direction. A method for manufacturing the semiconductor structure is also provided.

An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Gate drive apparatus and control method

Gate drive apparatus control method

A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Split-gate trench MOSFET

A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.

Thinned semiconductor chip with edge support

A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the V, R, and BV.

Self-aligned dual trench device

During fabrication of a semiconductor device, a width of semiconductor mesas between isolation trenches in the semiconductor device is varied in different regions. In particular, the width of the mesas is smaller in a termination region of the semiconductor device than in a cell or active region. When an oxide layer is subsequently grown, the semiconductor mesas between the trenches in the termination region are at least partially consumed so that the semiconductor mesas in the cell region and the termination region have different heights. Therefore, a contact photomask is not needed to isolate the semiconductor mesas in the termination region. Furthermore, after a planarization operation (such as chemical mechanical polishing), the semiconductor device may have a planar top surface than if contact holes are created. This may allow the metal layer deposited on top of the cell region and the termination region to be flat.

Trench schottky devices

A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Thin film transistor having highly dielectric organic layer

A SiC-based trench-type Schottky device is disclosed. The device includes: a SiC substrate having first and second surfaces; a first contact metal formed on the second surface and configured for forming an ohmic contact on the substrate; a drift layer formed on the first surface and including a cell region and a termination region enclosing the cell region; a plurality of first trenches with a first depth formed in the cell region; a plurality of second trenches with a second depth less than the first depth; a plurality of mesas formed in the substrate, each defined between neighboring ones of the trenches; an insulating layer formed on sidewalls and bottoms of the trenches; and a second contact metal formed on the mesas and the insulating layer, extending from the cell region to the termination region, and configured for forming a Schottky contact on the mesas of the substrate.

Growing community of inventors

Hsinchu, Taiwan

Chiao-Shun Chuang