Chartered Semiconductor Manufacturing Ltd (corporation)

Chian Yuh Sin

Simon Yew-Meng Chooi

Liang Choo Hsia

Fan Zhang

Tae Jong Lee

Huey Ming Chong

Xiaomei Bu

Kho Liep Chok

Luona Goh

Yee Mei Foong

Zainab Ismail

Vincent Sih

Ping Yu Ee

Yin-Min Felicia Goh

Cher Sian Chua

Meng Luo

Teck Wee Lim

Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.

Methods for elimination of arsenic based defects in semiconductor devices with isolation regions

A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

Integrated circuit with protective moat

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Singapore, Singapore

Chian Yuh Sin