Advanced Semiconductor Engineering, Inc.

Ase (shanghai) Inc.

Chian-Chi Lin

Wei-Chung Wang

Min-Lung Huang

Ching-Huei Su

Kuo-Chung Yee

Po-Jen Cheng

Jian-Wen Lo

Ho-Ming Tong

Teck-Chong Lee

Chao-Fu Weng

Kao-Ming Su

Song-Fu Yang

Chih-Huang Chang

Chih-nan Wei

Chia-Jung Tsai

Su Tao

Che-Ya Chou

Shih-Chang Lee

Kuo-Pin Yang

Shin-Hua Chao

Sung-Mao Wu

Yueh-Lung Lin

Hsueh-An Yang

A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.

Three-dimensional package and method of making the same

The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

Microelectromechanical microphone packaging system

A semiconductor chip package manufacturing method and a structure thereof are provided. The manufacturing method includes: providing a base having an image sensor chip and an encapsulant, in which the image sensor chip has pads and an active area; placing a transparent insulator on the active area; forming an insulation layer on an upper surface of the base; opening a plurality of openings to expose the pads; forming a plurality of through holes penetrating the insulation layer and the encapsulant outside of the image sensor chips; forming a metal layer on surfaces of the insulation layer, the openings, the pads and the through holes, and on a lower surface of the base, so as to extend the pads to the lower surface of the base; patterning the metal layer to expose a top area of the transparent insulator and remove a partial area of the metal layer on the lower surface of the base to form contacts; and sawing the base to form a package structure containing a single image sensor chip.

Semiconductor chip package manufacturing method and structure thereof

A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are 'inserted' into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.

Wire-bonding method for wire-bonding apparatus

A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying and conveying a substrate. The first pick-up device is for picking up one of the dies and placing each die on the arranging platform. The second pick-up device is for picking up the dies on the arranging platform and placing the dies on the substrate at the same time.

Two-stage die-bonding method for simultaneous die-bonding of multiple dies

A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Packaging substrate and manufacturing method thereof

A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.

A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer with passivation openings exposing the bonding pads is provided. Next, a first dielectric layer with first openings and second openings is disposed on the wafer. The first openings and second openings expose the bonding pads and the portions of the passivation layer respectively. Afterwards, a patterned first electrically conductive layer is formed over the first dielectric layer and the bonding pads. Then a second dielectric layer is formed over the first dielectric layer and the patterned first electrically conductive layer and exposes the patterned first conductive layer through the second openings to form a plurality of bump pads wherein the bump pads are electrically connected to bonding pads. Next, a second electrically conductive layer is formed over the second dielectric layer and the bump pads. Then, a plurality of bumps are formed on the portions of the second electrically conductive layer covering the bump pads. Finally, the bumps are reflowed and the portions of the second electrically conductive layer covered by the reflowed bumps are remained to form a patterned second electrically conductive layer.

Wafer level bumping process

A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside but also it can save cost due to the lead frame manufactured by a simple manufacturing processes. In addition, a manufacturing method of the multi-chips module package is provided.

Multi-chips module package and manufacturing method thereof

A multi-chips bumpless assembly package with a patterned conductive layer, a patterned dielectric layer and an insulation layer interposed between the chips is provided, which can shorten the distance of the electrical connection between the chips so as to upgrade the electrical performance of the assembly package and make the package thinner and thinner. Moreover, a manufacturing method thereof is also provided to form a package with high electrical performance.

Multi-chips bumpless assembly package and manufacturing method thereof

A thermal enhance multi-chips module (MCM) package mainly comprises a first package, a first carrier, a second package, a second carrier, an intermediate substrate and a cap-like heat spreader. The intermediate substrate has an opening. The first carrier and the second carrier are electrically connected to the first package and the second package respectively. The second package is accommodated in the opening and electrically connected to the first package via the first carrier, the second carrier and the intermediate carrier. The cap-like heat spreader has a supporting portion and an alignment portion wherein the supporting portion is connected to the alignment portion to define a cavity. The cavity not only accommodates the first package, the first carrier, the second package, the second carrier and the intermediate substrate but also provides alignment mechanism by the supporting portion and the alignment portion to prevent the dislocation after all the components of the thermal enhance MCM package are connected with each other. Furthermore, the first carrier has a first side and the second carrier has a second side. The first side and the second side both have grounding portions, for example recessed portions and metal layers, for providing a ground shielding of the first package and the second package against the outside. In addition, the grounding portions also provide thermal paths to increase the ability of the heat dissipation. Besides, a method for manufacturing the thermal enhance MCM package is provided.

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Tainan, Taiwan

Chian-Chi Lin