Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Delta Electronics, Inc.

Chia-Yuan Chang

Xiong-Fei Yu

Hui-Cheng Chang

Kuei-Lun Lin

Nang-Ping Tu

Chi On Chui

Cheng-Hao Hou

Kai-Cheng Chang

Wen-Ping Teng

Chi-On Chui

Che-Hao Chang

Te-Yang Lai

Kun-Yu Lee

Po-Ting Lin

Cheng-Chieh Liu

Tsung-Da Lin

Pei-Fang Liang

Yen-Fu Chen

Yung-Yuan Ho

Chia-Huang Wu

Yong-Nien Rao

Pin-Cha Hsu

Yong-Noen Rao

Yong-Nian Rau

Han-Pei Wang

A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.

Semiconductor device

A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Fin field effect transistor having conformal and non-conformal gate dielectric layers

A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

Triple layer high-k gate dielectric stack for workfunction engineering

A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.

Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.

Method for manufacturing semiconductor device

A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a first metal gate electrode and a second metal gate electrode. The n-channel and the p-channel are made of different materials. The first gate dielectric layer is present on at least opposite sidewalls of the n-channel. The second gate dielectric layer is present on at least opposite sidewalls of the p-channel. The first metal gate electrode is present on the first gate dielectric layer. The second metal gate electrode is present on the second gate dielectric layer. The first metal gate electrode and the second metal gate electrode are made of substantially the same material.

Semiconductor device and method of manufacturing the same

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

Semiconductor devices and FinFET devices having shielding layers

A manufacturing method of a thin fan comprises the steps of: providing a plastic material containing a plurality of metal particles; molding the plastic material into a housing; removing a part of a surface of the housing to form a circuit layout area at the housing; and forming a metal layer in the circuit layout area.

Thin fan and manufacturing method thereof

A transient current suppression device, which is applied to a fan, includes a filtering circuit, a delayed turn-on circuit and a forcibly electrical discharging circuit. The filtering circuit outputs a first voltage signal and a first current signal according to a first power signal. The delayed turn-on circuit is electrically connected with the filtering circuit. The delayed turn-on circuit provides a first discharging path for the first current signal according to a second power signal after a delayed time and outputs a second current signal. The forcibly electrical discharging circuit is electrically connected with the delayed turn-on circuit and the filtering circuit. The forcibly electrical discharging circuit provides a second discharging path for the second current signal according to the first voltage signal. Hence, the transient current suppression device can suppress the transient current effectively and rapidly.

Transient current suppression device and method

A plane type electric precipitator includes an electrode plate of plane shape, made of electricity-conducting material; a collecting plate, parallel to the electrode plate and made of electricity-conducting material; a plurality of electrode units, placed on the electrode plate and having tips; wherein direct electric voltage is applied between the electrode plate and the collecting plate, so that air passing through is exposed to high electric fields close to the tips of the electrode units, ionizing suspended particles and trapping ionized particles at the collecting plate, so that an air-cleaning effect results.

Planar electric precipitator

An adjustable eddy electrostatic precipitator, including a main body, an electrode array, an adjustable opening and a precipitating device. The main body has an inner space with an air guiding plate of helical shape, an entrance for air and an exit for air. The electrode array is placed close to the entrance, ionizing air as well as particles floating therein. The adjustable opening is located at the exit, having an adjustable aperture. The precipitating device is connected with a bias high voltage for adsorbing ionized particles. Air entering the main body through the entrance is ionized, ionizing particles floating therein. Ionized particles are driven towards a single zone and are collected depending on size and charge in an adjustable manner.

Adjustable eddy electrostatic precipitator

A method of testing a reflection-type LCD projector is disclosed. The present invention provides a method of testing the digital-circuit portion of the data drivers of the silicon wafer LCD of the reflection-type LCD projector, and a method of testing the panel pixel area of the silicon wafer LCD display. The present invention can be applied to LCD display panels manufactured by CMOS process and polysilicon thin film transistor process for the benefits of helping to resolve manufacturing issues during the development stage, thereby shortening the required production time schedule, and reducing the production cost.

Method for testing reflection LCD projector and display panel pixel area thereof

A method and apparatus for converting digital input signal to analog voltage are disclosed herein. The converting apparatus includes the following devices device. One of the pair of reference voltage selecting means is used to select a first voltage level as a first power source. Similarly, a second voltage level is selected as a second power source. The pair of controlled selectively coupling devices couples the first power source or the second power source as the charge power source responding to voltage level of every bit of the second portion of the digital input signal. The voltage cumulating device is used to generate the analog voltage by alternatively charging and redistributing the output capacitor with the first and the second capacitor. The foregoing method includes the following steps. At first, divide reference voltage levels into a first set and a second set of reference voltage levels. Then select a first and a second voltage level from the first and the second set of reference voltage levels as a first and a second power source respectively according to coding of a first portion of said digital input signal. Sequentially select the first power source or the second power source as a charge power source. The output capacitor is electrically coupled to the first storage capacitor or the second storage capacitor, then voltage on said output capacitor being equal to the analog voltage.

Serial pipeline DAC with Gamma correction function

A D/A converter with a Gamma correction circuit according to the invention is designed for C-DAC which utilizes multiplexers to obtain reference voltages. This D/A converter takes up much less space and has more simple structure than the conventional R-DAC and 2-divided C-DAC. Therefore, this D/A converter has advantages of simple design and low cost. Furthermore, users can freely define the shape of a Gamma correction conversion curve to thereby widen application areas by adjusting terminal voltages.

D/A converter with a gamma correction circuit

A thin-film transistor liquid-crystal display (TFT LCD) driver includes a shift register, a sample and hold circuit, a group block, and a controller. The shift register provides N graded sample clocks. Video signals are delivered to the group block via the sample and hold circuit through the control of the controller. The group block having n groups of N switches transfers a group of N pixel signals from the sample and hold circuit to the display. The display driver of the invention providing n.times.N output lines by using N processing units by virtue of the output distribution of the group block not only reduces circuit space, but also lowers the power consumption requirements.

Growing community of inventors

Hsinchu, Taiwan

Chia-Yuan Chang