Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Ying Lee

Jyu-Horng Shieh

Ching-Feng Fu

Yu-Chan Yen

Huan-Just Lin

Ming-Chung Liang

Kuan-Wei Huang

Chun-Hung Lee

De-Fang Chen

Ru-Gun Liu

Chih-Ming Lai

Shih-Ming Chang

Ming-Feng Shieh

Ken-Hsien Hsieh

Hong-Jie Yang

Shau-Lin Shue

Chung-Ju Lee

Tien-I Bao

Tsai-Sheng Gau

Cheng-Hsiung Tsai

Ming-Hsi Yeh

Kuo-Bin Huang

Chun-Neng Lin

Po-Nan Yeh

U-Ting Chiu

Meng-Chun Chang

Yu-Shih Wang

Kuen-Ming Liou

Meng Jhe Tsai

Hao Chiang

Chuan Chang

Syun-Ming Jang Jang

Tze-Liang Lee

Tai-Chun Huang

Ming-Hsing Tsai

Chih-Yuan Ting

Kuei-Shun Chen

Yen-Chun Huang

Bor Chiuan Hsieh

Yu Shih Wang

Meng-Wei Chen

Yuan-Hsiang Lung

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Fin field-effect transistor device and method

A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Method of breaking through etch stop layer

An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Self-aligned interconnect with protection layer

The present disclosure, in some embodiments, relates to an integrated circuit structure. The integrated circuit structure includes a substrate and a hard mask over the substrate. The hard mask has sidewalls that form a first opening and a second opening exposing an upper surface of the substrate. A block mask is arranged on the hard mask and is set back from the sidewalls of the hard mask. Spacers are disposed over the block mask and have sidewalls that define a spacer opening exposing an upper surface of the block mask. The block mask extends from directly below the spacers to laterally past the sidewalls of the spacers.

Double patterning method

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

Spacer etching process for integrated circuit design

The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.

Cut first self-aligned litho-etch patterning

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.

The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

Cut last self-aligned litho-etch patterning

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

Self-aligned nanowire formation using double patterning

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

Growing community of inventors

Taipei, Taiwan

Chia-Ying Lee