Taiwan Semiconductor Manufacturing Comp. Ltd.

Accton Technology Corporation

Chia-Wei Ho

Chun-Wei Hsu

Liang-Guang Chen

Chi-Jen Liu

Kei-Wei Chen

Yi-Sheng Lin

Chi-Hsiang Shen

Yang-Chun Cheng

William Weilun Hong

Te-Ming Kung

Li-Chieh Wu

Kuo-Hsiu Wei

Ting-Hsun Chang

Ling-Fu Nieh

Pinlei Edmund Chu

Chia Hsuan Lee

Jian-Ci Lin

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Metal heterojunction structure with capping metal layer

Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Methods of forming an abrasive slurry and methods for chemical- mechanical polishing

A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.

Vias with metal caps for underlying conductive lines

Semiconductor devices and methods of forming are provided. In some embodiments the semiconductor device includes a substrate, and a dielectric layer over the substrate. A first conductive feature is included in the dielectric layer, the first conductive feature comprising a first number of material layers. A second conductive feature is included in the dielectric layer, the second conductive feature comprising a second number of material layers, where the second number is higher than the first number. A first electrical connector is included overlying the first conductive feature.

Semiconductor devices formed using multiple planarization processes

The current disclosure describes a metal surface chemical mechanical polishing technique. A complex agent or micelle is included in the metal CMP slurry. The complex agent bonds with the oxidizer contained in the CMP slurry to form a complex, e.g., a supramolecular assembly, with an oxidizer molecule in the core of the assembly and surrounded by the complex agent molecule(s). The formed complexes have an enlarged size.

CMP slurry and CMP method

Methods of forming an abrasive slurry and methods for chemical-mechanical polishing

Semiconductor devices and methods of forming are provided. In some embodiments the method includes forming a dielectric layer over a substrate and patterning the dielectric layer to form a first recess. The method may also include depositing a first layer in the first recess and depositing a second layer over the first layer, the second layer being different than the first layer. The method may also include performing a first chemical mechanical polish (CMP) process on the second layer using a first oxidizer and performing a second CMP process on remaining portions of the second layer and the first layer using the first oxidizer. The method may also include forming a first conductive element over the remaining portions of the first layer after the second CMP polish is performed.

Methods of forming semiconductor devices using multiple planarization processes

A footing structure including a plurality of recess holes at a bottom side of a hub, each recess hole having two springy retaining pieces at two opposite sides, and a plurality of metal receptacles respectively mounted in the recess holes and holding a respective magnetic element therein, each metal receptacle having two flanges extended from two opposite side notches thereof and respectively forced into engagement with the springy retaining pieces of the corresponding recess hole.

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Kaohsiung, Taiwan

Chia-Wei Ho