Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chia-Ping Lai

Jen-Yuan Chang

Chien-Chang Lee

Chung-Chuan Tseng

Chien-Ying Wu

Sui-Ying Hsu

Chen-Hao Huang

Chiao-Chi Wang

Yuehying Lee

Hau-Yan Lu

Tzu-Chung Tsai

Li-Hsin Chu

Yeh-Hsun Fang

Chen-Hsiang Hung

Yu-Hsiang Tsai

Tsung-Yang Hsieh

Wen-Feng Kuo

Yueh-Ying Lee

Cheng-Kang Huang

Wen-Chung Lu

Mei-Shih Kuo

Shih-Chang Chen

Yu-Wei Chen

Alice Huang

Hsin-Hung Chen

Chun-Tse Tsai

Yueh Ying Lee

Szu-Chien Tseng

Zong-Jie Wu

Chih-Ai Huang

Capacitors for use in semiconductor devices including a plurality of first trenches in a first region of a substrate, the first trenches extending in a first direction, a plurality of second trenches in the first region of the substrate, the second trenches extending in a second direction other than the first direction, with the adjacent second trenches and first trenches cooperating to define protruding structures and island structures having an upper surface that is at or below a plane defined by a portion of an upper surface of a substrate surrounding the first region with a series of film pairs including a dielectric layer and a conductive layer formed in the first and second trenches and the protruding and island structures.

Integrated circuit including trench capacitor

A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Semiconductor package including test line structure

A semiconductor device includes: a photodiode formed in a substrate; and at least one transistor having a gate feature that comprises a first portion and a second portion coupled to an end of the first portion, the first portion disposed above and extending along a major surface of the substrate and the second portion extending from the major surface of the substrate into the substrate, wherein the photodiode and the at least one transistor at least partially form a pixel.

Image sensor device

An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

Fan-out packages providing enhanced mechanical strength and methods for forming the same

A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

Semiconductor die including guard ring structure and three-dimensional device structure including the same

The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a metallic shield extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; and removing a portion of the redistribution layer to form a first opening over the photoelectric device. A metallic shield extending at least partially through the redistribution layer and surrounding the first opening is formed during the formation of the redistribution layer.

Semiconductor structure and method for forming the same

Various embodiments of the present disclosure are directed towards methods for forming an image sensor in which a device layer overlies and has a different semiconductor material than a substrate and in which the device layer has high crystalline quality. Some embodiments of the methods include: epitaxially growing the device layer on the substrate; patterning the device layer to form a trench dividing the device layer into mesa structures corresponding to pixels; forming an inter-pixel dielectric layer filling the trench and separating the mesa structures; and forming photodetectors in the mesa structures. Other embodiments of the methods include: depositing the inter-pixel dielectric layer over the substrate; patterning the inter-pixel dielectric layer to form cavities corresponding to the pixels; epitaxially growing the mesa structures in the cavities; and forming the photodetectors in the mesa structures.

Methods for forming image sensors

A method includes forming a plurality of openings extending into a substrate from a front surface of the substrate. The substrate includes a first semiconductor material. Each of the plurality of openings has a curve-based bottom surface. The method includes filling the plurality of openings with a second semiconductor material. The second semiconductor material is different from the first semiconductor material. The method includes forming a plurality of pixels that are configured to sense light in the plurality of openings, respectively, using the second semiconductor material.

Image sensor device and methods of forming the same

A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.

Three-dimensional integrated circuit

An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Optical integrated circuit structure including edge coupling protective features and method of forming same

A method for forming a semiconductor structure includes receiving a die; forming a dielectric layer to surround the die; removing a portion of the dielectric layer to form a first recess; disposing a first light blocking layer within the first recess; applying a dielectric paste over the first light blocking layer; removing a portion of the dielectric paste to form a second recess; disposing a second light blocking layer within the second recess; disposing a photoelectric device over the first light blocking layer and the second light blocking layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; removing a portion of the redistribution layer to form a third recess over the photoelectric device; and coupling a light-conducting member to the photoelectric device through the third recess; wherein the second light blocking layer is separated from the first light blocking layer and the photoelectric device.

Method for forming a semiconductor die and a photoelectric device integrated in a same package

A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Semiconductor die including through substrate via barrier structure and methods for forming the same

A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same

A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Growing community of inventors

Hsinchu, Taiwan

Chia-Ping Lai