Intel Corporation

Chia-Pin Chiu

Weng Hong Teh

Zhimin Wan

John Stephen Guzek

Deepak Kulkarni

Johanna M Swan

Robert Starkston

Aleksandar Aleksov

Sujit Sharan

Debendra Mallik

Henning Braunisch

Stefanie M Lotz

Chandra Mohan Jha

Ravi V Mahajan

Hinmeng Au

Robert L Sankman

Shankar Devasenathipathy

Omkar G Karhade

Je-Young Chang

Zhiguo Qian

Mathew J Manusharow

Gregory Martin Chrysler

Tim Tri Hoang

Ravindranath Vithal Mahajan

Chuan Hu

Ioan Sauciuc

Russell S Aoki

Kinya Ichikawa

Charles A Gealer

Gregory Turturro

Kaveh Hosseini

Tannaz Harirchian

Qing Ma

Pooya Tadayon

Robert M Nickerson

Hong Xie

Ravi S Prasher

Deepak Goyal

Jin Yang

Anna M Prakash

Weihua Tang

Steven A Klein

Kyle Yazzie

Anthony P Valpiani

Peng Li

Tolga Acikalin

Feras Eid

Patrick R Morrow

Paul B Fischer

Peng T Li

Nitin A Deshpande

Yuan-Liang Li

Alan M Myers

William J Lambert

Eric Jin Li

Kyu Oh Lee

Eric DiStefano

Rajiv K Mongia

Yoshihiro Tomita

Cheng Xu

Yikang Deng

David Shia

Himanshu Pokharna

Junnan Zhao

Pramod Malatkar

Edvin Cetegen

Joe F Walczyk

Gilroy J Vandentop

Chong Zhang

Sandeep B Sane

Ying Wang

Patrick D Boyd

Kenneth Foust

Yiqun Bai

Xiaoqian Li

Tae Young Yang

Mark J Gallina

Mohit Mamodia

Kelly P Lofgreen

Mohanraj Prabhugoud

Sridhar V Machiroutu

Raj Nair

Joseph B Petrini

Michael Zack Eckblad

Jessica Gullbrand

Shan Zhong

Lloyd L Pollard, Ii

Anandaroop Bhattacharya

James C Shipley

Ching-Ping Janet Shen

Asako Toda

Mark Saltas

Xuejiao Hu

Mostafa A Aghazadeh

Shaorong Zhou

Shrenik Kothari

Tyler N Osborn

Suzana Prstic

Edward W Jaeck

Amanuel M Abebaw

A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

Reduced bridge structure for a photonic integrated circuit

Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

On-cavity photonic integrated circuit (OCPIC) to achieve the most undercut real estate for effective thermal tuning

Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

Temperature sensor to achieve thermal stabilization of micro-ring resonator (MRR) in an open cavity photonic integrated circuit (OCPIC)

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Undercut design with a bonded base cover for friendly assembly and effective thermal tuning of micro-ring resonator (MRR) in open cavity photonic integrated chips (OCPIC)

An electronic assembly, such as an integrated circuit package, may be formed comprising a package substrate and a photonic integrated circuit device attached thereto, wherein the package substrate includes a heat dissipation structure disposed therein. A back surface of the photonic integrated circuit device may thermally coupled to the heat dissipation structure within the package substrate for the removal of heat from the photonic integrated circuit device, which allows for access to an active surface of the photonic integrated circuit device for the attachment of fiber optic cables and eliminates the need for a heat dissipation device to be thermally attached to the active surface of the photonic integrated circuit device.

Heat dissipation structures for optical communication devices

Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

High density substrate routing in package

Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.

TEC-embedded dummy die to cool the bottom die edge hotspot

An apparatus is described. The apparatus includes a packaged semiconductor device. The packaged semiconductor device having an integrated heat spreader, wherein, a boiling enhancement structure exists on the integrated heat spreader without a block mass residing between the boiling enhancement structure and the integrated heat spreader. The boiling enhancement structure has a structured non-planar surface to promote bubble nucleation in an immersion cooling system.

Boiling enhancement structures for immersion cooled electronic systems

Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

Hybrid interposer of glass and silicon to reduce thermal crosstalk

Embodiments disclosed herein include dual sided cooling architectures for laser packages. In an embodiment, an electronic package comprises a package substrate, and a laser chip attached to the package substrate. In an embodiment, the laser chip has a first surface and a second surface opposite from the first surface. In an embodiment, an interposer is disposed over the laser chip, where the interposer overhangs an edge of the laser chip. In an embodiment, the electronic package further comprises an interconnect between the interposer and the package substrate.

Package designs to enable dual-sided cooling on a laser chip

A multi-chip package includes a substrate () having a first side (), an opposing second side (), and a third side () that extends from the first side to the second side, a first die () attached to the first side of the substrate and a second die () attached to the first side of the substrate, and a bridge () adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity () in the substrate or between the substrate and a die layer (). The bridge may constitute an active die and may be attached to the substrate using wirebonds ().

Multi-chip package and method of providing die-to-die interconnects in same

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Localized high density substrate routing

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate.

Completely encapsulated optical multi chip package

Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

Thermally conductive slugs/active dies to improve cooling of stacked bottom dies

Growing community of inventors

Tempe, AZ, United States of America

Chia-Pin Chiu