Orient Semiconductor Electronics, Limited

National Cheng-Kung University

Inotera Memories, Inc.

Chia-Ming Yang

Yueh-Ming Tung

In-Gann Chen

Jung-Wei Chen

Kuo-Yang Sun

Shu-Min Chou

Chien-Chi Lee

Guan-Lin Pan

Shu-Fen Liang

Jian-De Leu

Chung-Yuan Lee

Steve Lien-Chung Hsu

Hung-Chang Liao

Jer-Chyi Wang

Chang-Shu Kuo

Chih-Yuan Hsiao

Shih-Wen Tseng

Wen-Lo Shieh

Hsin-Huei Chen

Regan Stanley Tsui

Ming-Chi Chao

Chung-Lun Lee

Jin-Chun Wen

Ke-Miao Lu

Wei-Ping Lee

Wei-Mao Hung

Ying-Chuan Li

Kai-Lun Chiang

Chen-Fa Tsai

Po-Tsung Hsieh

Chao-Sung Lai

Shih-Hsien Liu

Yuan-Wei Liu

Eric Lahaug

Yao-Hsien Wang

Ya-Wen Tsai

Chen-Kang Wei

Hung-Cheng Chen

Ping Kao

Ping-Hua Chu

Hao-Hsun Chang

Ming Yean

Ya-Wen Chuang

Yi-Wei Chuang

Hsiao-Lung Chiang

The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

Electronic package including electromagnetic shielding structure and method of manufacture

The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.

Semiconductor package comprising heat spreader and manufacturing method thereof

A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1&#x2dc;1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.

Method of fabricating high-power module

The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.

Manufacturing method of semiconductor package comprising heat spreader

A high temperature reaction system includes a reaction tube including a heating space, a discharge unit, a cooling unit, a feeding unit and an observation and analysis unit. The discharge unit is disposed opposite to an inlet of the heating space and has a discharge space communicating the heating space, and an observation window and a discharge opening which communicate the discharge space. The cooling unit has a cooling space communicating the discharge opening. The feeding unit includes a carrier holding a sample, and a moving module for moving the carrier and the sample. The observation and analysis unit includes an image capture module and an analysis module for analyzing gas released by the sample.

High temperature reaction system

A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.

Chip packaging device and alignment bonding method thereof

A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.

Memory cell having a recessed gate and manufacturing method thereof

The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region.

Wafer and film coating method of using the same

A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.

DRAM with dopant stop layer and method of fabricating the same

A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.

Memory card with electrostatic discharge protection and manufacturing method thereof

A package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame.

Package Structure

In a semiconductor device, a semiconductor chip is mounted on an inner seat body of a heat-dissipating frame mounted on a top surface of a dielectric substrate. Each of multiple bonding wires interconnects electrically one of multiple contact pads on the semiconductor chip and a corresponding one of multiple first conductive contacts on the top surface of the substrate so as to establish electrical connection between the contact pads on the semiconductor chip and multiple second conductive contacts on a bottom surface of the substrate via the first conductive contacts and circuit traces of the substrate. An encapsulant encapsulates the bonding wires, the semiconductor chip, and the inner seat body, a portion of an outer frame body of the heat-dissipating frame, and multiple that interconnect portions interconnecting heat-conductively the inner seat body and the outer frame body.

Semiconductor device with heat-dissipating capability

An improved structure of a pin platform of an integrated circuit having a pin platform body including a chip seat and a plurality of leading plates having their end portions being concentrated on the chip seat and the chip seat being connected to the pin platform body via the connection plate, characterized in that the surrounding of the chip seat is provided with a framing side, and the framing side is connected to a connection plate, and the surface of the chip seat is smaller than the connection surface of the IC to be installed, and the size of the framing side is larger than the size of the connection face of the IC. Therefore, a high performance greenery package is obtained and the ground wire of the IC can be soldered to the framing side, which provides a smooth connection and a communication.

Structure of a pin platform for integrated circuit

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Kaohsiung, Taiwan

Chia-Ming Yang