Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Kuei Hsu

Shin-Puu Jeng

Po-Yao Lin

Ming-Chih Yew

Shu-Shen Yeh

Chin-Hua Wang

Che-Chia Yang

Po-Chen Lai

Po-Hao Tsai

Li-Ling Liao

Shuo-Mao Chen

Feng-Cheng Hsu

Yu-Sheng Lin

Tsung-Yen Lee

Chia-Hsiang Lin

Yu Chen Lee

Hsien-Wei Chen

Po-Yao Chuang

Meng-Liang Lin

Shih-Ting Hung

Jing-Ye Juang

Shang-Lun Tsai

Chien Hung Chen

Chien-Shen Chen

Yu-Chen Lee

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure comprising fan-out bonding pads, and a first underfill material portion, a packaging substrate comprising chip-side bonding pads, solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads, a second underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the second underfill material portion and having a Young's modulus that is lower than a Young's modulus of the second underfill material portion.

Underfill cushion films for packaging substrates and methods of forming the same

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a surface of the substrate. The ring structure is located over the surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the surface of the substrate and a top surface opposite the bottom surface. The ring structure includes recesses recessed from and located on the top surface, wherein the recesses are arranged corresponding to the corners of the substrate. The adhesive layer is interposed between the bottom surface of the ring structure and the surface of the substrate.

Semiconductor device package having warpage control and method of forming the same

A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.

Dual-underfill encapsulation for packaging and methods of forming the same

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Organic interposer including intra-die structural reinforcement structures and methods of forming the same

A semiconductor package includes a die, a first conductive pattern, a second conductive pattern and first and second under-ball metallurgy (UBM) patterns. The first conductive pattern and the second conductive pattern are disposed below and electrically connected to the die, wherein the first conductive pattern has an ellipse-like shape, and the second conductive pattern has a circular shape. The first and second under-ball metallurgy (UBM) patterns correspond to the first and second conductive patterns, the first conductive pattern has a first length, the second conductive pattern has a second length, the first and second UBM patterns have a third length, wherein the first length is larger than the third length and the second length is smaller than the third length.

Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape

A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Eccentric via structures for stress reduction

A package assembly includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and attached to the package substrate. The package lid includes an outer lid including an outer lid material and including an outer lid plate portion. The package lid further includes an inner lid including an inner lid material different than the outer lid material and including an inner lid plate portion attached to a bottom surface of the outer lid plate portion.

Package assembly lid and methods for forming the same

A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

Package assembly including lid with additional stress mitigating feet and methods of making the same

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

High efficiency heat dissipation using discrete thermal interface material films

A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

Metallization structure

A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

Package structure and methods of manufacturing the same

A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

Semiconductor die package with multi-lid structures and method for forming the same

A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Semiconductor package and method of manufacturing the same

In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

Three-dimensional integrated circuit packages and methods of forming the same

A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

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Hsinchu, Taiwan

Chia-Kuei Hsu