Powertech Technology Inc.

Chia-Jen Chou

Ting-Feng Su

Li-Chih Fang

Yong-Cheng Chuang

Kuo-Ting Lin

Yi-hsin Chen

Guang-Ren Shen

A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error.

Package method of a modular stacked semiconductor package

A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

Semiconductor device package with a stress relax pattern

A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Fan-out wafer level package structure

A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.

Heat-dissipating semiconductor package for lessening package warpage

A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

Growing community of inventors

Hsinchu County, Taiwan

Chia-Jen Chou