Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia-Jen Cheng

Hsiu-Mei Yu

Li-Hsin Tseng

Po-Yao Lin

Ming-Chih Yew

Fu-Jen Li

Tzu-Han Lin

Chun-Yen Lo

Boe Su

Huei-Mei Yu

Shih-Ming Chen

Tjandra Winata Karta

Wen-Hsiang Tseng

Chien-Min Lin

Shih-Ming Chin

Simon W Lu

Chien-Tung Yu

Gil Huang

Chih-Min Tseng

Tung-Wen Hsieh

Blenny Chang

Owen Chen

Yu-Lung Feng

Ken Sun

Chih Yang Chan

Mon-Chin Tsai

Jian-Wen Luo

Hsiu-Mei Yo

Hui-Mei Yu

Daniel Yang

Ching-Chiang Wu

Li-Chuan Huang

Fang-Chuang Liu

An interconnect structure includes a first substrate including a first surface, a second surface opposite to the first surface, a cavity extended through the first substrate, and a first recess extended from the second surface towards the first surface; a second substrate disposed opposite to the second surface of the first substrate; an electronic device disposed within the cavity; a first polymeric layer disposed over the first surface and within the cavity of the first substrate; and a second polymeric layer disposed between the first substrate and the second substrate and within the first recess.

Interconnect structure and manufacturing method thereof

A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Electrical connection for chip scale packaging

A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.

Crosstalk-free WLCSP structure for high frequency application

An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.

Back end integrated WLCSP structure without aluminum pads

A method for removing dry film resist (DFR) from a fine pitch solder bump array on a semiconductor wafer provides for pre-soaking the wafer in a chemical bath then turbulently exposing the wafer to a chemical solution, both steps taking place in batch processing with the wafers processed in a vertical position. The wafers are then individually processed through a chemical spinning operation in which a chemical solution is dispensed from a spray nozzle while motion such as spinning is imparted the horizontally disposed wafer. The spin speed of the chemical spraying process may then be increased to accelerate physical removal of residue. Deionized water rinsing and spin-drying provide a solder bump array void of any DFR or other residuals.

Method of fine pitch bump stripping

A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening. The first and second photoresist layers are removed and the solder material is reflown to create a solder ball of increased height.

Method for forming solder bumps of increased height

Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.

Bump structure

A method for fabricating a pad redistribution layer. First, at least one bonding pad exposed by a first passivation layer is provided. A diffusion barrier layer and a seed layer are then formed over the first passivation layer and the bonding pad. A patterned mask layer is then formed over the seed layer to expose a portion thereof over the bonding pad, and a metal layer is then formed thereon. A sacrificial layer is then formed over the substrate and the sacrificial layer over the patterned mask layer is removed. The conductive film exposed by the metal layer and the remaining sacrificial layer is then removed, leaving a pad redistribution layer for the bonding pad.

Method for fabricating pad redistribution layer

A method for improving an adhesion bond between a solder material and an under bump metallization (UBM) layer including providing at least two UBM layers overlying a chip bonding pad including an uppermost UBM layer forming a contact layer for forming a solder bump thereon; depositing a solder bump precursor material overlying the contact layer to form a solder column; exposing the sidewalls of the solder column to include the contact layer sidewalls; oxidizing the contact layer sidewalls to form a contact layer sidewall oxide at a temperature lower than the melting point of the solder bump precursor material; and forming a solder bump by reflowing the precursor material to wet the contact layer surface to exclude the contact layer sidewalls.

Method for improving a solder bump adhesion bond to a UBM contact layer

Growing community of inventors

Taoyuan, Taiwan

Chia-Jen Cheng