Taiwan Semiconductor Manufacturing Comp. Ltd.

Chia Hui Hsu

Kuan Liang Wu

Shiaw-Lin Chi

Wei-Chin Shiau

Chen Hsin Hsiung

Yu-Jye Lan

Wen Jen Chiu

Ming Tsang Yu

The present invention provides an Intelligent Engineering Data Analysis (I-EDA) system and method to help prevent low wafer yield and prevent occurrences of abnormal events. The I-EDA has a non-conforming wafer tracing (NCWT) system that operates to correlate occurrences of abnormal events with low wafer yield. The method generally has the steps of performing a fabrication operation on wafers disposed within a wafer lot; determining if an abnormal event occurred while performing the fabrication operation on the wafers disposed within the wafer lot; using a NCWT to determine a statistical correlation between an occurrence of an abnormal event and a wafer yield of the wafers being processed during the occurrence of the abnormal event if the abnormal event occurred during processing of the wafers disposed within the wafer lot; and using the determined statistical correlation to analyze the fabrication process and thereby improve wafer yield.

System and method to analyze low yield of wafers caused by abnormal lot events

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Hsin-Chu, Taiwan

Chia Hui Hsu