Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Lite-on Technology Corporation

Compal Electronics, Inc.

Other

Dell Products Inc.

Sunplus Technology Co., Ltd.

Qisda Corporation

Lite-on Electronics (guangzhou) Limited

Chang Chun Petrochemical Co., Ltd.

Tpk Glass Solutions (xiamen) Inc.

Chia-Hao Hsu

Chia-Chen Chen

Kuo-Chiang Ting

Ting-Yu Yeh

Chia-Ching Huang

Tu-Hao Yu

Shang-Yun Hou

Tai-Yu Chen

Chi-Hsi Wu

Weiming Chris Chen

Chia-Huang Chan

Shinn-Sheng Yu

Hsing-Chih Liu

Yao-Pang Hsu

You-Yu Chen

Kai-Cheng Chao

Wen-Chih Chiou

Anthony Yen

Jeng-Horng Chen

Chia-Jen Chen

Yung-Chi Lin

Yu Chao Lin

Chi-Yuan Chen

Shiann-Tsong Tsai

Chung-Fa Lee

Shang-Chieh Chien

Yen-Cheng Lu

Sheng-Liang Kuo

Bo-Jiun Yang

Yu-Nan Tsai

Chun-Lai Hsiao

Chao-Cheng Chen

Chih-Ming Chen

Pei-Cheng Hsu

Tzung-Chi Fu

Tsung-Yu Chen

Kuan-Yu Huang

Christopher A Torres

Anthony J Sanchez

Kevin M Turchin

Enoch Chen

Jui-Ching Wu

Shu-Chia Hsu

Tzu-Hsiang Chen

Kuo-Yu Wu

Pin-Tso Lin

Chia-Hsin Chen

Tzu-Wei Kao

Yu-Ming Lin

Jen-Cheng Liu

John Trevor Morrison

Po-Chung Cheng

Chih-Tsung Shih

Shou-Gwo Wuu

Tsang-Jiuh Wu

Yu-Cheng Chen

Hsin-Hung Lee

Chien-Hsien Tseng

Wen-Sung Hsu

Kai-Wen Cheng

Feng-Jia Shiu

Yi-Tzu Chen

Wan-Yu Lee

Wei-Hao Lan

Jia-Ming Chen

Hao-I Yang

Ya-Ting Chang

Cheng-Shiue Jan

Tsiao-Chen Wu

Tsung-Hsien Tsai

Shu-Hao Chang

Chia-Yu Lee

Chien-Chu Chen

Ching-Hung Cheng

Che-Hung Kuo

Ching-Juinn Huang

Chen-Hsin Chang

Tzu-Li Lee

Chien-Chih Lee

Geng-Cing Lin

Jen-Ti Peng

Hsin-Che Hsieh

Cheng-Fan Wang

Ying-Yu Chen

Shan-Yu Wu

Chiu Jung Tsen

Hung-Lin Chou

Wen-Lung Lin

Li-Ching Lin

Yu-Hao Hu

Cheng-Jen Chang

Sheng-Feng Yeh

Tao-Hsin Chen

Jen-Chieh Yang

Chien-Ming Chiu

Tung-Yi Wu

Wei-Huan Lee

Cheng-Lung Wu

Shih-Yen Chiu

Pi-Cheng Hsiao

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Encapsulated package including device dies connected via interconnect die

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.

A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The liquid metal is formed between the cover and the electronic component.

Semiconductor device and manufacturing method thereof

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

Integrated circuit packages

A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

Semiconductor package having liquid-cooling lid

A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

Method for manufacturing semiconductor package structure

A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure

A portable information handling system supports a flexible OLED display film over housing portions rotationally coupled by a hinge by folding the OLED display film over the hinge. Hinge brackets that couple to the housing portions each have a gear member with a semicircular shape gear inner circumference that engages a gear subassembly of the hinge main body. Hinge bracket rotation translates through the gear subassembly for synchronized housing rotation. The hinge main body has first and second semicircular portions with a smooth surface defined to accept the outer circumference smooth surface of the gear member semicircular shape at first and second rotation axes about which the hinge brackets pivot so that the display film has space to fold in the closed position.

Gear synchronized dual axis pivot hinge

A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

Semiconductor package structure

Methods of forming integrated circuit packages

A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.

Semiconductor package with heat dissipation films and manufacturing method thereof

A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

Growing community of inventors

Hsinchu, Taiwan

Chia-Hao Hsu