Taiwan Semiconductor Manufacturing Comp. Ltd.

Taiwan Semiconductoh Manufactuhing Company Limited

Chia-En Huang

Yih Wang

Meng-Sheng Chang

Meng-Han Lin

Jung-Ping Yang

Yi-Ching Liu

Cheng Hung Lee

Chih-Chieh Chiu

Fu-An Wu

I-Han Huang

Sai-Hooi Yeong

Yi-Hsun Chiu

Hong-Chen Cheng

Yen-Huei Chen

Han-Jong Chia

Jui-Che Tsai

Gu-Huan Li

Chun-Ying Lee

Hidehiro Fujiwara

Shao-Yu Chou

Yao-Jen Yang

Hao-I Yang

Chieh Lee

Yu-Ming Lin

Shih-Lien Linus Lu

Yu-Hao Hsu

Chien-Ying Chen

Geng-Cing Lin

Tung-Cheng Chang

Bo-Feng Young

Ping-Wei Wang

Sheng-Chen Wang

Atul Katoch

Ching-Wei Wu

Chia-Ta Yu

Hsin-Wen Su

Kao-Cheng Lin

Chen-Lin Yang

Ming-Hung Chang

Saman M I Adham

Donald George Mikan, Jr

Lien-Jung Hung

Chien-Yu Huang

Martin Liu

Ming-Chien Tsai

Tsung-Yung Chang

Chun-Jiun Dai

Hektor Huang

Uppu Sharath Chandra

Jonathan Tsung-Yung Chang

Shih-Hao Lin

Chia-Cheng Chen

Wun-Jie Lin

Wen-Hsing Hsieh

Perng-Fei Yuh

Haruki Mori

Chien-Chi Tien

Hsiao-Lan Yang

Chun Chung Su

Feng-Lun Chen

Hua-Tai Shieh

Ze-Sian Lu

Yi-Ching Chang

Kuan-Lun Cheng

Chung-Te Lin

Ching-Wei Tsai

Feng-Cheng Yang

Po-Hsiang Huang

Jam-Wem Lee

Katherine H Chiang

Jen-Yuan Chang

Kuo-Ji Chen

Hau-Tai Shieh

Chiting Cheng

Yu-Kuan Lin

Yu-Xuan Huang

Yangsyu Lin

Yen-Jen Chen

Wen-Sheh Huang

Cheng-Hung Lee

Ya-Yun Cheng

Yu-Hsiang Chen

Ming-Yen Chuang

Yun-Feng Kao

Ming-Yi Lee

Peng-Chun Liou

Tao-Yi Hung

Yi-Hung Tsai

Wan-Hsueh Cheng

Wei-Shuo Kao

Hsing-Leo Tsai

Ya-Hui Wu

Philex Ming-Yan Fan

Ling-Chang Hu

Chang Jen-Yuan

Jimmy Lee

Rose Tseng

A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

One-time-programmable memory device including an antifuse structure and methods of forming the same

Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

Switches to reduce routing rails of memory system

A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

Three-dimensional ferroelectric memory device with width-differentiated channel and ferroelectric segments

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Memory devices and methods of manufacturing thereof

A semiconductor device includes a first memory array which includes a first memory string including a plurality of first memory cells arranged in a vertical direction. The first memory array further includes a first conductive structure operatively coupled to the first memory string that extends through the first memory array in the vertical direction. The semiconductor device further includes a second memory array including a second memory string including a plurality of second memory cells arranged in the vertical direction. The second memory array further includes a second conductive structure operatively coupled to the second memory string that extends through the second memory array in the vertical direction. The semiconductor device further includes a bowl-shaped conductive structure interposed between the first and second memory arrays, and configured to operatively couple the first conductive structure to the second conductive structure.

Semiconductor memory devices and methods of manufacturing thereof

A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

Memory device with reduced area

A memory device is disclosed. The memory device includes a transistor. The memory device includes a resistor electrically coupled to the transistor, the transistor and the resistor forming an electrical fuse (eFuse) memory cell. The memory device includes a plurality of interconnect structures formed over a source/drain structure of the transistor. The memory device includes a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures. The resistor is formed of titanium nitride (TiN).

MIM efuse memory devices and memory array using a metal-based layer between structures

A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.

Semiconductor memory devices with dielectric fin structures

A memory device includes an anti-fuse cell array having a plurality of anti-fuse cells, each of the plurality of anti-fuse cells having a first transistor and a second transistor connected to the first transistor. A first terminal of the first transistor is connected to a bit line and the bit line is a buried rail formed in a substrate of the first transistor and the second transistor.

Method for protecting anti-fuse cell

A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.

Semiconductor memory devices with different word lines

A method of making a semiconductor die includes forming, over a substrate, a stack including insulating layers and sacrificial layers alternatively on top of each other; replacing a portion of first sacrificial layers located in a first portion of the stack to form first gate layers; forming first channel layers extending in a first direction in the first portion; forming first memory layers extending in the first direction in the first portion; replacing a portion of second sacrificial layers located in a second portion of the stack to form second gate layers; forming second channel layers extending in the first direction in the second portion; and forming second memory layers extending in the first direction in the second portion.

Semiconductor dies including low and high workfunction semiconductor devices

A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Memory systems with vertical integration

A semiconductor device includes a first transistor, a second transistor, and a memory component. The first transistor includes a first silicon layer, a high-k gate dielectric layer above the first silicon layer, a first metal gate above the high-k gate dielectric layer, and first source/drain regions within the first silicon layer. The second transistor includes a second silicon layer, a first silicon oxide layer above the second silicon layer, a plurality of first doped silicon gates above the first silicon oxide layer, a plurality of second doped silicon gates above the first silicon oxide layer and alternately arranged with the plurality of first doped silicon gates, and second source/drain regions within the second silicon layer. The memory component is above the first and second transistors, and electrically coupled to the second source or drain region.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Semiconductor memory devices with different doping types

A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Semiconductor memory devices with diode-connected MOS

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Xinfeng, China

Chia-En Huang