United Semiconductor Corp.

United Microelectronics Corp.

Other

Chia-Chieh Yu

Yueh-Feng Ho

Ching-Hsing Hsieh

Jy-Hwang Lin

Ta-Cheng Chou

A method of reworking a photoresist layer. A silicon chip having an insulation layer, a bottom anti-reflection coating and a photoresist layer thereon is provided. The photoresist layer has already been light-exposed and developed. A wet etching operation is carried out to remove a large portion of the photoresist layer. A low-temperature plasma treatment incapable of transforming the anti-reflection coating structure is conducted to remove the hardened residual photoresist material. A new photoresist layer is formed over the bottom anti-reflection coating.

Method of reworking photoresist layer

An improved method of forming a via on a semiconductor substrate forms a conductive line thereon and then forms an inter-metal dielectric layer over the conductive line. A patterned photoresist layer is formed on the inter-metal dielectric layer. A portion of the inter-metal dielectric layer is removed to expose the conductive line using the photoresist layer as a mask to form a via hole, wherein the via hole is subsequently used to form a via. A high density plasma process is performed to remove the photoresist layer. The photoresist layer remaining on the substrate is removed with a solvent.

Method for forming a via

A method of forming a dual damascene structure. A first dielectric layer is formed over a substrate, and then the first dielectric layer is planarized. The first dielectric layer is etched to form a dual damascene opening that includes a via opening and a trench. The via opening exposes a conductive layer in the substrate. A metallic is formed in the via openings and the trenches so that a metallic interconnect and a via are formed at the same time. A cap layer is formed on the metallic layer. An additional etching stop layer may form on the cap layer and the substrate. A second dielectric layer is formed over the substrate. The second dielectric layer is etched to form a via opening that exposes a portion of the cap layer.

Method for forming dual damascene structure

A damascene process, applicable to a semiconductor substrate, with a patterned first mask layer formed thereon. A part of the substrate not covered by the first mask layer is exposed, while a first dielectric layer is formed on the exposed part of the substrate. The first mask is then removed to form a first opening in the first dielectric layer. A conformal barrier layer is formed on the substrate and the first dielectric layer, followed by filling the first opening with a metal plug. Alternatively, a dual damascene process is disclosed where a second patterned mask layer is formed in first opening and covers a part of the first dielectric layer, while a part of the first dielectric layer is exposed. A second dielectric layer is formed on the exposed part of the first dielectric layer. The second patterned mask layer is removed to form a second opening and to expose the first opening. Consequently, the conformal barrier layer is formed on the substrate and the dielectric layers, before filling the openings with the metal plug.

Damascene process

A method for fabricating a passivation layer of a gate electrode. A conductive layer, a mask layer and a patterned photoresist layer are sequentially formed on a gate oxide layer. The photoresists layer is thick enough to precisely transfer a pattern from the photoresist layer to the mask layer. The photoresist layer is stripped, and an etching step is performed to transfer the patterned of the mask layer onto the conductive layer, so as to form a gate electrode. During the etching step, a corner of the mask layer is partly truncated to form a cap layer with an arc shape corner. A conformal liner oxide layer is formed on the cap layer and a sidewall of the gate electrode. A spacer is further formed on the conformal liner oxide layer extending over a top surface of the gate electrode.

Method of fabricating passivation of gate electrode

A method for forming a high-quality aluminum-copper alloy pattern over a semiconductor substrate. The method first forms an aluminum-copper alloy layer over a semiconductor substrate, and then performs a rapid thermal processing operation to remelt copper extracts into the alloy bulk. Subsequently, a photoresist layer is formed over the alloy layer. Finally, the alloy layer is etched to transfer the pattern from the photoresist layer to the metallic alloy layer. Unlike a conventional method that can lead to abnormal conduction due to the presence of extracts that are difficult to etch, this invention uses a thermal operation to remove the extracts before etching is conducted. Hence, the masking effect due to etching is mostly prevented.

Method for forming metallic layer using inspected mask

The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer. A metal layer is formed to fill the via hole by chemical vapor deposition.

Method of manufacturing interconnect

A method for removing a photoresist. A substrate having a wire on the substrate and a flowable oxide layer over the substrate and a patterned photoresist over the flowable oxide layer is provided. A plasma etching step is performed by using an additional gas mixed with oxygen as a source to remove the photoresist layer.

Method for removing photoresist

A surface treatment method for bonding pad is described, in which a passivation layer is formed on a bonding pad and an opening is formed within the passivation by a plasma etching process. The bonding pad is corroded by the etching plasma containing fluorine during the etching process. The bonding pad is rinsed with deionized water comprising carbon dioxide to reduce the effects of the corrosion phenomenon.

Surface treatment for bonding pad

A method for improving the differential etching rate of forming vias in a metallic layer by the addition of a nitrogen plasma processing operation into the conventional metal etching operation. The nitrogen plasma processing operation facilitates the formation of aggregates through a chemical reaction between gaseous nitrogen and metal. The aggregates are able to lower the etching rate of metal in such a way that its effect on a wide-open via is more than on a narrow-dense via. Hence, microloading effect on the etching rate is greatly improved.

Method for improving differential etching rate of a metallic layer

Disclosed is a method of etching which makes the quantitative analysis possible and easier. In the prior art, chemical plasma etching is mainly by ion bombardment, and the tool used to observe the metal bulk is transmission electron microscopy (TEM), so it is very difficult and complicated to execute quantitative analysis. By using chemical plasma etching, the metal precipitate will be left almost all at the end of etching. Scanning electron microscopy (SEM) is used instead of TEM to perform the quantitative analysis.

Growing community of inventors

Taipei Hsien, Taiwan

Chia-Chieh Yu