Au Optronics Corporation

Globalwafers Co., Ltd.

Realtek Semiconductor Inc.

Chia-Chi Tsai

Ta-Wen Liao

Han-Tu Lin

Chih-Hung Shih

Chih-Chun Yang

Ming-Yuan Huang

Shang-Chi Wang

I-Ching Li

Chia-Ming Chang

Chien-Huang Liao

Kuo-Lung Fang

Pin-Miao Liu

Tien-Lun Ting

Chun-Fan Chung

Ming-Hung Tu

Hsiang-Chih Hsiao

Yu-Chieh Chen

Chun-Yi Chiang

Han-Zong Wu

Zong-Long Jhang

Che-Yung Lai

Chou-Huan Yu

Han-Tang Chou

Chen-Pang Tung

Jun-Kai Chang

Miao-Pei Chen

Wen-Ching Hsu

Yi-Sheng Cheng

Ming-Cheng Chiang

Tsung-Peng Chuang

Chin-Yueh Liao

Cheng-Pin Chang

Li-Lung Kao

Chia-Jung Lee

Shiun-Chang Jan

Chan-Ju Wen

Bo-Ting Lin

Provided is a wafer jig including a bottom wall and a ring-shaped side wall. The bottom wall has a supporting surface. The ring-shaped side wall is connected to a periphery of the bottom wall. The ring-shaped side wall includes at least two step portions. The two step portions include a first step portion and a second step portion. The first step portion is connected between the supporting surface and the second step portion, and the first step portion protrudes along a direction toward a center of the bottom wall. The ring-shaped side wall surrounds the center. In addition, a wafer structure and a wafer processing method are also provided.

Wafer jig, wafer structure and wafer processing method

A method for identifying a wafer is provided, which includes the following steps. A marked frame is obtained from a wafer inspection picture. A gray scale index corresponding to the marked frame is calculated based on a gray scale value corresponding to each of multiple pixels included in the marked frame. The gray scale index indicates a proportion of pixels whose gray scale values are greater than a specified value. Whether a trace pattern in the marked frame is a scratch or a grain boundary is determined based on the gray scale index.

Method for identifying wafer

A wafer surface defect inspection method and a wafer surface defect inspection apparatus are provided. The method includes the following steps. Scanning information of a wafer is received, and the scanning information includes multiple scanning parameters. At least one reference point of the scanning information is determined, and path information is generated according to the at least one reference point and a reference value. Multiple first scanning parameters corresponding to the path information in the scanning parameters are obtained according to the path information to generate a curve chart. According to the curve chart, it is determined whether the wafer has a defect, and a defect type of the defect is determined.

Wafer surface defect inspection method and apparatus thereof

A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.

Material analysis method

The disclosure provides a wafer inspection method and wafer inspection apparatus. The method includes: receive scanning information of at least one wafer, wherein the scanning information includes a plurality of haze values; the scanning information is divided into a plurality of information blocks according to the unit block, and the feature value of each of the plurality of information blocks is calculated according to the plurality of haze values included in each of the plurality of information blocks; and converting the feature value into a color value according to the haze upper threshold and the haze lower threshold, generating the color value corresponding to the at least one wafer according to the converted color value according to the feature value, whereby the color graph displays the texture content of the at least one wafer.

Wafer inspection method and apparatus thereof

A device is provided that includes a plurality of signal processing paths coupled in parallel, an adding circuit and an amplifier circuit. The number of the signal processing paths is N and each of the signal processing paths receives a same input signal to generate an output analog signal after a signal processing is performed, wherein each of the signal processing paths at least includes a DAC circuit and the signal processing at least includes a digital to analog conversion corresponding to the DAC circuit. The adding circuit adds the output analog signal generated from each of the signal processing paths to generate a total output analog signal. The amplifier circuit receives the total output analog signal to adjust a signal intensity of the total output analog signal according to a gain to generate an output audio signal, wherein the gain is 1/N.

Audio playback device and method

In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Flat display apparatus and control circuit and method for controlling the same

A combo-plug detecting circuit for use in an audio CODEC is provided. The combo-plug detecting circuit is used to determine the contact configuration of the audio plug, to ensure that the audio plug belonging to the differential structure can be compatible with the audio CODEC.

Combo-plug detecting circuit and operational method thereof

A circuit for driving a loudspeaker is disclosed. The circuit includes: a signal generator connected to the loudspeaker, generating a first signal comprising a first pulse with positive value and a second pulse with negative value; a detection circuit connected to the loudspeaker, detecting a second signal produced by the loudspeaker in response to the first signal; and a processing circuit connected to the signal generator and the detection circuit, calculating the impedance of the loudspeaker according to the second signal; wherein each pulse width of the first and second pulses is between 100 ns and 900 ns.

Circuit and method for driving a loudspeaker

A method for fabricating a pixel structure is disclosed. A substrate is provided. A first conductive layer is formed on the substrate, and a first shadow mask exposing a portion of the first conductive layer is disposed over the first conductive layer. Laser is used to irradiate the first conductive layer for removing the part of the first conductive layer and forming a gate. A gate dielectric layer is formed on the substrate to cover the gate. A channel layer is formed on the gate dielectric layer over the gate. A source and a drain are formed on the channel layer and respectively above both sides of the gate. A patterned passivation layer is formed to cover the channel layer and expose the drain. An electrode material layer is formed to cover the patterned passivation layer and the exposed drain.

Method for fabricating pixel structure

A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.

A method for fabricating a pixel structure is provided. First, a substrate having an active device formed thereon is provided. The active device has a gate, a gate dielectric layer, and a semiconductor layer having a channel, a source, and a drain region. Then, a dielectric layer is formed to cover the active device, and a photo-resist layer having a first photo-resist block and a second photo-resist block thinner than the first photo-resist block is formed on the dielectric layer. The second photo-resist block has openings above the source and the drain region, respectively. The source and the drain regions are exposed by removing part of the dielectric layer with the photo-resist layer as a mask. A second metal layer is formed after removing the second photo-resist block. A source and a drain are formed after removing the first photo-resist block. A pixel electrode connected to the drain is formed.

A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost.

A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.

Growing community of inventors

Hsinchu, Taiwan

Chia-Chi Tsai