Cadence Design Systems, Inc.

Lucent Technologies Inc.

At&t Bell Laboratories

Cadence Design Systens, Inc.

Chi-Yuan Lo

Shun-Lin Su

Mikhail Khapaev

Yue-Zhong Shu

Debaprosad Dutt

Doowan Paik

Kuang-Wei Chiang

Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical&#x2014;around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

Method to adaptively calculate resistor mesh in IC designs

Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Extracting capacitance and resistance from FinFET devices

A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.

Method of compressing data for use in performing VLSI mask layout

A method is described which reduces the size of the constraint graph used in assembling cells into a tiled module for integrated circuit manufacture. The smaller size significantly reduces the amount of time required to assemble the cells appropriately.

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Basking Ridge, NJ, United States of America

Chi-Yuan Lo