Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Tsinghua University

Chi-Yuan Chen

Teng-Chun Tsai

Li-Ting Wang

Cheng-Tung Lin

Wei-Jung Lin

Huicheng Chang

Hong-Mao Lee

Chia-Han Lai

Huang-Yi Huang

Kuo-Yin Lin

Wan-Chun Pan

Yao-Pang Hsu

Chun-I Tsai

Chia-Hao Hsu

Tai-Yu Chen

Shiann-Tsong Tsai

Hsing-Chih Liu

Chung-Fa Lee

Chi-Hsuan Ni

Kuo-Cheng Ching

Hsiang-Pi Chang

Ming-Liang Yen

Yen-Yu Chen

Shi Ning Ju

Chun-Hsiung Lin

Wen-Sung Hsu

Hongfa Luan

Ya-Jui Hsieh

Shih-Chao Chiu

Chih-Hao Wang

Ching-Wei Tsai

Wen-Chun Huang

Ming-Chyi Liu

Ta-Jen Yu

Hui-Cheng Chang

Bing-Hung Chen

Yi-Lin Tsai

Yu-Chen Hu

Cary Chia-Chiung Lo

Li-Lan Wu

Sang-Mao Chiu

An antenna-in-module package-on-package includes an antenna package having a top surface and a bottom surface opposing the top surface. The antenna package includes a radiative antenna element on the bottom surface. A chip package is mounted on the top surface of the antenna package. The chip package includes a semiconductor chip. Conductive elements are disposed between the antenna package and the chip package to electrically interconnect the chip package and the antenna package. A radiative antenna element is disposed on the bottom surface of the antenna package. At least one air trench is disposed on the bottom surface of the antenna package.

Antenna-in-module package-on-package with air trenches

A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate.

Lidded semiconductor package

A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure

A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.

Contact structure and formation thereof

A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

Semiconductor package with rigid under bump metallurgy (UBM) stack

Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.

Systems and methods for gap filling improvement

A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.

Integrating junction formation of transistors with contact formation

Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.

Opening fill process and structures formed thereby

Opening fill process and structure formed thereby

Growing community of inventors

Hsinchu, Taiwan

Chi-Yuan Chen