Advanced Semiconductor Engineering, Inc.

Chi-Yu Wang

Ming Hsien Chu

Yuan-Ting Lin

Chin-Li Kao

Tai-Yuan Huang

Wei-Hong Lai

Che Wei Chang

A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.

Semiconductor device package and method for manufacturing the same

A semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is disposed on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is disposed on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.

Semiconductor device and method for manufacturing the same

A wiring structure includes a redistribution layer and an electrical pad. The redistribution layer includes a passivation layer and a metal layer. The metal layer is embedded in the passivation layer, and the passivation layer defines an opening to expose a portion of the metal layer. The electrical pad is disposed in the opening of the passivation layer and on the metal layer. The electrical pad includes a seed layer, a conductive layer, a barrier layer and an anti-oxidation layer.

Semiconductor device structure having semiconductor die bonded to redistribution layer via electrical pad with barrier layer

A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle &#x3b8;relative to a direction of extension of the body portion.

Semiconductor devices and methods of manufacturing the same

A wafer level package mainly comprises a semiconductor wafer and a plurality of bonding pads disposed on the active surface of the wafer. It is characterized in that there is a protection layer formed on the back surface of the wafer, wherein the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the bonding pads. In such a manner, the protection layer will prevent the back surface of the wafer from being contaminated with the solder material. Moreover, when a UBM layer is further provided on the bonding pad, the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the UBM layer.

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Kaohsiung, Taiwan

Chi-Yu Wang