Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Yang Yu

Chin-Liang Chen

Kuan-Lin Ho

Yu-Min Liang

Chien-Hsun Lee

Jiun-Yi Wu

Hai-Ming Chen

Jung Wei Cheng

Jung-Wei Cheng

Wei-Yu Chen

Yu-min Liang

Chih-Hao Lin

Chien-Kuo Chang

Wen-Lin Chen

Tsung-Ding Wang

Hsin-Yu Pan

Yu-Chih Liu

Chen-Hua Douglas Yu

Jiun Yi Wu

Hao-Cheng Hou

Chien-Chang Lin

Yen-Fu Su

Nien-Fang Wu

Jing Ruei Lu

Jung Tsung Cheng

A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.

Package structure and forming method thereof

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.

Package structure and manufacturing method thereof

An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Electronic component and manufacturing method thereof

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Die corner removal for underfill crack suppression in semiconductor die packaging

A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Semiconductor package

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Semiconductor package and manufacturing method thereof

A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Semiconductor structure and manufacturing method thereof

Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure.

Package structure and method of forming the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.

An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

Integrated fan-out package and manufacturing method thereof

A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.

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Taoyuan, Taiwan

Chi-Yang Yu