Samsung Electronics Co., Ltd.

Chi-wook Kim

Sung-min Seo

Min-Soo Kim

Hyung-Chan Choi

Jae-Young Lee

Sung-Hoon Kim

Jun-Hyung Kim

Sang-Seok Kang

Byung-Hoon Jeong

Kyu-Hyoun Kim

Jong-hyun Choi

Jung-Hwa Lee

Han-gu Sohn

Byong-mo Moon

Doo-young Kim

Jae-woong Lee

Soo-Bong Chang

Kyung-woo Kang

Youn-Sik Park

Chan-yong Lee

Jae-hoon Kim

Moo-Sung Chae

Je-Min Yu

Jin-Kyoung Jung

Geun-hee Cho

Myeong-o Kim

Dong-ryul Ryu

Soon-hong Ahn

Tai-young Ko

Joon-Hyuk Kwon

A bridge defect detecting method performed in a semiconductor memory device that includes a plurality of memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers connected to the bit lines, includes the operations of: enabling a first sense amplifier and a second sense amplifier; keeping the first sense amplifier in an enabled state and disabling the second sense amplifier; enabling the second sense amplifier, and detecting a bridge defect between the first memory cell and the second memory cell by reading data from a first memory cell of a first bit line connected to the first sense amplifier and a second memory cell of a second bit line connected to the second sense amplifier.

Semiconductor memory device capable of detecting bridge defects and bridge defect detecting method performed in the semiconductor memory device

A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

Methods and devices for regulating the timing of control signals in integrated circuit memory devices

A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Semiconductor memory device having local sense amplifier

A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Circuits/methods for electrically isolating fuses in integrated circuits

An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active. The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Synchronous output buffer, synchronous memory device and method of testing access time

A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

Semiconductor memory device and method of arranging a decoupling capacitor thereof

Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.

Semiconductor memory device and method of arranging signal and power lines thereof

Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Shared decoupling capacitance

Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.

Delay stage insensitive to operating voltage and delay circuit including the same

Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

Semiconductor memory device and layout method thereof

An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage generating circuit controls a reference voltage level according to an operating mode of the semiconductor memory device such that the operating characteristics of the semiconductor memory device can be improved in some operating modes and power dissipation can be minimized in other operating modes.

Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level

A double data rate ('DDR') synchronous dynamic random access memory ('SDRAM') semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (&#x201c;DLL&#x201d;) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

Double data rate synchronous dynamic random access memory semiconductor device

Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation

Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Growing community of inventors

Gyeonggi-do, South Korea

Chi-wook Kim