Macronix International Co., Ltd.

Chi-Tung Huang

Kuang-Chao Chen

Yung-Tai Hung

Tuung Luoh

Chun-Fu Chen

Pei-Ren Jeng

Ling-Wuu Yang

Chun-Chung Huang

Yun-Chi Yang

Ping-Yi Chang

Wan-Yi Liu

Sheng-Hui Hsieh

Yuhturng Liu

Candy Jiang

Hsing-Hua Chiu

A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.

Systems and methods for back end of line processing of semiconductor circuits

A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.

Method for symmetric deposition of metal layer

A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the first polished surface with a rinse composition to provide a rinsed surface; and polishing the rinsed surface by providing a second polishing composition to provide a second polished surface.

Two-step chemical mechanical polishing process

A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.

Methods for metal ARC layer formation

A method for improving accuracy of determining polish endpoint of chemical mechanical polish (CMP) process is provided. The method is performed before the CMP process. First, a test wafer with a to-be-polished layer and a material layer under the to-be-polished layer is provided. Then, a test beam with a wavelength is provided to irradiate the test wafer. The CMP process is performed to the test wafer to remove the to-be-polished layer until the material layer is exposed while the reflection of the test beam during the polish process is continuously detected. The reflection tendency is detected when the to-be-polished layer is to be completely removed and when the CMP process reaches the interface between the to-be-polished layer and the material layer. If the reflection tendency is gradually weakened, the test beam with the wavelength is chosen for the subsequent polish process.

Chemical mechanical polish process and method for improving accuracy of determining polish endpoint thereof

A process is described for creating a uniformly thick layer of titanium, cobalt, or nickel silicide over a layer of polysilicon that has features or a non-planar topography. A dual layer of metal is deposited onto patterned polysilicon such that the first layer covers the bottoms and tops of the non-planar topography and the second layer covers the sidewalls and tops of the non-planar topography. By heating the metal, etching away any un-reacted metal, and heating the result a second time, a metal silicide layer of uniform thickness, reduced stress and reduced resistivity is formed.

Method of forming a metal silicide layer on non-planar-topography polysilicon

A method for manufacturing contact plug is disclosed. A dielectric layer is formed over a substrate having a conductive region. A contact opening is formed in the dielectric layer and exposing the conductive region within the opening. A first refractory metal layer is formed over the dielectric layer, and the sidewalls and bottom of the contact opening. A first refractory metal nitride layer is formed on the first refractory metal layer. A first plasma treatment step is carried out to transform the first refractory metal nitride layer into a first metal nitrided barrier layer. A thermal-process is carried out to form metal silicide on the conductive region. A second refractory metal nitride layer is formed on the first metal nitride barrier layer. A second plasma treatment step is carried out to transform the second refractory metal nitride layer into a second metal nitrided barrier layer. A conductive metal layer is deposited over the resulting structure and then the top surface is planarized to remove portions of the conductive metal layer, the second metal nitride barrier layer, the first metal nitride barrier layer, and the first refractory metal layer until the dielectric layer is exposed.

Method of fabricating contact plug

A method for planarizing the dielectric layer of a flash memory device, wherein the method is applied on substrate of a flash memory device having a plurality of gate structures formed thereon and a protective layer is formed on the gate structures. A dielectric layer is formed on the substrate, filling the space between the gate structures and covering the protective layer. Using the protective layer as a polishing endpoint layer, a fixed base and a polishing slurry that does not contain metal ions are used to chemical mechanically polish and to planarize the dielectric layer. The fixed base includes a base and evenly distributed polishing abrasives fixed onto the base.

Method for planarizing a dielectric layer of a flash memory device

A wafer carrier used for a chemical mechanical device has a polishing head and a pad conditioner. The polishing head has a retainer ring secured to a bottom of the polishing head to hold a wafer. The pad conditioner can be fixed on a surface of the retainer ring, attached to side surfaces of the retainer ring, or embedded in the retainer ring, such that the pad conditioner and the polishing head can be integrally formed.

Wafer carrier used for chemical mechanic polishing

A method of processing dielectric layers in FeRAM and the structure of the like are provided. A FeRAM having a barrier layer, a first electrode, a second electrode, and a ferroelectric material is sandwiched between two layers of gradient dielectric layers. These gradient dielectric layers have changing refraction index from one side to the other side. As a result, these gradient dielectric layers prevent hydrogen from damaging the FeRAM structure. The change in refraction index is achieved by adjusting the ratio and deposition power of the SiH4 and N2O during plasma enhanced chemical vapor deposition of the gradient dielectric layers.

Method of processing dielectric layer in ferroelectric RAM and structure of the like

The present invention provides a passivation film on a semiconductor wafer. The semiconductor wafer comprises a dielectric layer and a patterned conductive layer on the dielectric layer. The passivation film comprises a high density plasma (HDP) oxide layer positioned on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer, a silicon nitride layer positioned on the HDP oxide layer, and a water-resistant layer positioned on the silicon nitride layer. The HDP oxide layer possesses good gap filling abilities to fill the spaces inside the conductive layer.

Passivation film on a semiconductor wafer

A method of planarizing a dielectric layer of a flash memory. In the present invention, a high selectivity slurry is used to planarize a dielectric layer of a flash memory. The high selectivity slurry comprises a Ceria-polishing-particle-containing slurry having CeO and a planarity selective additive having polycarboxylate. The concentration of CeO in the Ceria-polishing-particle-containing slurry is 5 wt % within a tolerance around 25% and the concentration of polycarboxylate in the planarity selective additive is 1-10 wt %.

Method for planarizing dielectric layer of flash memory

A method of fabricating a shallow trench isolation structure. A pad oxide layer, a mask layer, a dielectric anti-reflection coating layer and a cap oxide layer are formed on a substrate sequentially. A trench is formed in the substrate. A liner oxide layer is formed along a surface of the trench. An isolation layer is formed over the substrate to fill the trench. Using the mask layer as a polishing endpoint, the insulation layer, the dielectric anti-reflection coating layer and the cap oxide layer over the mask layer are removed. The thickness of the mask layer is controlled within a first fixed range, and the thickness of the dielectric anti-reflection coating layer is controlled, within a second fixed range, such that the light source of the optical endpoint detection system can produce a maximum reflected light signal. The mask layer and the pad oxide layer are then removed.

Method of fabricating shallow trench isolation

A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

Growing community of inventors

Hsinchu, Taiwan

Chi-Tung Huang