International Business Machines Corporation

Sematech, Inc.

Sv Probe Pte. Ltd.

Chi Shih Chang

William T Chen

Ajit Kumar Trivedi

Majid Ghafghaichi

John Balyoz

John A Palmieri

Teh-Sen Jen

Donald B Mooney

Barry C Fox

Frank Daniel Egitto

Subahu Dhirubhai Desai

Robert A Martone

Keith K Ho

Phillip A Hartley

Scott A Versprille

Robert D Schoening

Louis J Shaffer

Roy T Mulcahy

Robert J Haskins, Jr

Debra A Gernhart

Voya Rista Markovich

John M Lauffer

Bahadir Tunaboylu

David W Dranchak

James R Petrozello

Thomas G Macek

Ronald W Knepper

Michael Joseph Johnson

Joseph G Hoffarth

Shakir A Abbas

Stephen F Newton

George J Saxenmeyer, Jr

John P Wiley

Keith A Snyder

Jonathan James Hurd

Fletcher W Chapin

Raymond A Busacco

Leo B Freeman, Jr

Craig Neal Johnston

Rod A Smith

A method for manufacturing a ceramic device is provided. The ceramic device comprises a ceramic layer. A polyimide layer is on the ceramic layer. The polyimide layer has disposed therein a plurality of copper vias. Each copper via is in physical contact with the ceramic layer. A plurality of pads are formed on the polyimide layer. Each of the plurality of pads is in physical contact with a copper via of the plurality of copper vias. In this way, the pads are supported by a continuous copper arrangement, thereby providing greater support for the probe pads than if the probe pads were supported by the polyimide layer, as the mechanical strength of polyimide layer is lower than the mechanical strength of copper.

Probe pad structure in a ceramic space transformer

The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Placement of sacrificial solder balls underneath the PBGA substrate

The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTE's is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTE's reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.

Proper choice of the encapsulant volumetric CTE for different PGBA substrates

Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination

A transformer comprises a printed circuit board having elongated conductors printed thereon, a ferrite core having a bottom mounted onto the printed circuit board and a flex circuit. The flex circuit comprises a dielectric sheet and elongated conductors printed on both faces of the sheet. The flex circuit is contoured around a top and sides of the core. The conductors of the flex circuit are surface bonded to respective conductors of the printed circuit board to form a series of primary windings and a series of secondary windings around the core. Provision of the upper portions of the windings by means of the flex circuit is economical because it does not require handling of discrete conductor portions.

Transformer formed in conjunction with printed circuit board

A self-supporting redistribution structure for directly mounting a semi-conductor chip to a multilayer electronic substrate is separately fabricated and then laminated to the multilayer substrate. The redistribution structure comprises a dielectric layer having plated vias communicating between its two major surfaces, redistribution lines and input/output pads on its upper major surface and joining patterns on its lower margin surface for electrical connection with the multilayer substrate. The metal plating in the plated vias of the redistribution device connects respective input/output pads on the upper surface of the redistribution structures with the joining patterns on its lower major surface. Input/output pads define an even (planar) topography with the redistribution lines to facilitate flip chip joining.

Process for making planar redistribution structure

Construction of PBGA substrate for flip chip packing

Planar redistribution structure and printed wiring device

A system supplies power to and controls the frequency of electronic circuitry. The system comprises a DC source for supplying power to the electronic circuitry and a voltage controlled oscillator powered by the DC source. An output of the oscillator provides a system clock for the electronic circuitry such that as a voltage of the DC source continuously drops, the operating voltage of the electronic circuitry and oscillator continuously drops and the frequency of the system clock continuously drops in a manner corresponding to the continuous drop in operating voltage. Thus, the oscillator supplies an operating frequency tailored to the operating voltage to permit the electronic circuitry to operate at high speed.

System for extending operating time of a battery-operated electronic

Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) 'IF . . . THEN . . . ' production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Method and apparatus for the cross-sectional design of multi-layer

An electrical connector for interconnecting a pair of circuit members (e.g., a circuit board and module), which, in one embodiment, includes a housing, at least one flexible circuit within the housing and a spring means attached to the flexible circuit at two spaced locations for exerting force against the flexible circuit to cause the circuit to engage respective conductive pads on the circuit members when the circuit members are moved toward each other (e.g., compressed). The shape of the spring means conforms substantially to the portion of the flexible circuit between the locations of attachment. In another embodiment, a connector for interconnecting such circuit members includes a housing adapted for being located between both members and at least one elongated, compressible contact member in the housing and including conductive end portions for engaging the circuit members. The contact occupies a first, prestressed position before engagement and is adapted for moving to a second, compressed position during the engagement. The conductive end portions of the flexible circuit in the first embodiment and the contact member in the second embodiment preferably comprise a plurality of dendrites for providing enhanced connections.

High density connector

A multilayered circuit board assembly which includes a plurality of layered subassemblies each having electrically conducting wiring and at least one through hole therein. A first of these subassemblies possesses a greater wiring dnesity than the others while a second subassembly possesses a lesser resistance (and wiring density) than the others. In one example, several (e.g. at least four) such layered subassemblies may be included in the overall assembly such that those layers located along one side of the board may possess substantially greater wiring densities than the layers on the other side of the board while those layers on said other side will in turn possess lesser resistance (and greater current capacities). There are also described at least three methods for making the above multilayered circuit board assembly. Such a structure may be utilized in supercomputer applications.

High density circuit board and method of making same

Master image chip organization technique or method

Growing community of inventors

Austin, TX, United States of America

Chi Shih Chang