Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Ming Chen

Chung-Yi Yu

Po-Chun Liu

Chia-Shiung Tsai

Chen-Hao Chiang

Han-Chin Chiu

Kuei-Ming Chen

Xiaomeng Chen

Ho-Yung David Hwang

Cheng-Yuan Tsai

Fu-Wei Yao

Ru-Liang Lee

Min-Chang Ching

Ming Chyi Liu

Hung-Ta Lin

Chung-Yen Chou

Sheng-De Liu

Ping-Yin Liu

Jiun-Lei Jerry Yu

Chun-Feng Nieh

King-Yuen Wong

Yeong-Jyh Lin

Chih-Wen Hsiung

Che-Ming Chang

Chung-Chieh Hsu

Chin-Cheng Chang

Ming-Chang Ching

Shih-Chang Liu

Alexander Kalnitsky

Yung-Chang Chang

Yuan-Tai Tseng

Eugene I-Chun Chen

Yao-Chung Chang

Hsieh Ching Pei

Chia-Shiung Tsa

Various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. The first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. The first pair of source/drain regions comprise a first dopant. The diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. A doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.

Diffusion barrier layer for source and drain structures to increase transistor performance

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Rough buffer layer for group III-V devices on silicon

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Source/drains in semiconductor devices and methods of forming thereof

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.

Gallium nitride drain structures and methods of forming the same

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Method of implanting dopants into a group III-nitride structure and device formed

A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

Method for forming SOI substrate

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

A semiconductor device includes a doped substrate and a seed layer in direct contact with the substrate. The seed layer includes a first seed sublayer having a first lattice structure. The first seed layer is doped with carbon. The seed layer further includes a second seed sublayer over the first see layer, wherein the second seed layer has a second lattice structure. The semiconductor device further includes a graded layer in direct contact with the seed layer. The graded layer includes a first graded sublayer including AlGaN having a first Al:Ga ratio; a second graded sublayer including AlGaN having a second Al:Ga ratio different from the first Al:Ga ratio; and a third graded sublayer over including AlGaN having a third Al:Ga ratio different from the second Al:Ga ratio. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer.

Semiconductor device having doped seed layer and method of manufacturing the same

A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.

Semiconductor structure having sets of III-V compound layers and method of forming

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Zhubei, Taiwan

Chi-Ming Chen