Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Chi-Liang Kuo

Hsiang-Huan Lee

Shau-Lin Shue

Chao-Hsien Peng

Ming-Han Lee

Cheng-Hung Yu

Tz-Jun Kuo

A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.

Method of manufacturing a semiconductor device

In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

Via pre-fill on back-end-of-the-line interconnect layer

The present disclosure relates to a method of forming a back-end-of-the-line metal interconnect layer. The method is performed by depositing one or more self-assembled monolayers on a semiconductor substrate to define a metal interconnect layer area. A metal interconnect layer having a plurality of metal structures is formed on the semiconductor substrate within the metal interconnect layer area. An inter-level dielectric layer is then formed onto the surface of the semiconductor substrate in areas between the plurality of metal structures.

Back end of the line (BEOL) interconnect scheme

The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.

A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug.

Method of fabricating copper damascene

A structure, a fabrication method and an application of an overlay mark. The overlay mark structure has an outer mark and an inner mark. The outer mark encloses a cross area that has two central axes. The inner mark has four strip patterns arranged in two central axes and extend outwardly towards four directions from the central part of the closed cross area.

Growing community of inventors

Hsinchu, Taiwan

Chi-Liang Kuo