International Business Machines Corporation

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Siemens Microelectronics Limited

Chi-Hua Yang

Tomio Katata

Hideaki Aochi

Kenneth Parker Rodbell

Ronald G Filippi

Takamasa Usui

Darryl D Restaino

Munir D Naeem

Patrick William Dehaven

Masaki Narita

Virinder Grewal

Stuart M Burns

Bruno Spuler

Virinder S Grewal

Hans W Poetzlberger

Volker B Laux

Rosemary Christie

Walter W Kocon

A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.

High throughput A1-Cu thin film sputtering process on small contact via

Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used. Contact holes are made through a dielectric to conductors in a substrate by the same method, and desired cross sections are obtained by using a second resist mask and a selective etch for the polysilicon followed by a selective etch for the dielectric. These structures can be stacked and suitable interconnections made by the described method. Contact holes to gate electrodes can be etched using the basic process.

Etching high aspect contact holes in solid state devices

RIE of metallization is achieved at low power and low pressure using Cl.sub.2 and HCl as reactant species by creating a transformer coupled plasma with power applied to electrodes positioned both above and below a substrate with metallization thereon to be etched. Three layer metallizations which include bulk aluminum or aluminum alloy sandwiched between barrier layers made from, for example, Ti/TiN, are etched in a three step process wherein relatively lower quantities of Cl.sub.2 are used in the plasma during etching of the barrier layers and relatively higher quantities of Cl.sub.2 are used during etching of the bulk aluminum or aluminum alloy layer. The ratio of etchants Cl.sub.2 and HCl and an inert gas, such as N.sub.2 are controlled in a manner such that a very thin side wall layer (10-100 .ANG.) of reaction byproducts created during RIE are deposited on the side walls of trenches formed in the metallization during etching. The side wall layer improves the isotropic nature of the etch such that submicron metallization lines with defect free side walls are formed. Hydrogen (H.sub.2) can be added to the plasma and will act to reduce corrosion.

Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal

A metallization structure is fabricated by depositing an underlayer of a group IVA metal having a thickness of about 90 to about 110 angstroms, and depositing a layer of aluminum and/or an aluminum alloy. The metallization structure obtained exhibits enhanced electromigration and is highly textured and is especially suitable for forming electrical connections or wiring.

Process for fabricating a metallization structure

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Yorktown, NY, United States of America

Chi-Hua Yang