Azurewave Technologies, Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chi-Hsing Hsu

Kuan-Lun Cheng

Ching-Wei Tsai

Sai-Hooi Yeong

Chih-Hao Wang

Chun-Yu Lu

Jiun-Jia Huang

Tetsu Ohtou

Chih-Yu Chang

Min Cao

Chih-Chien Chen

Ming-Che Kuo

Kuo-Cheng Ching

Tzer-Min Shen

Ching-Wei Liu

Chin-Chien Chen

Ming-Shun Chen

A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Negative capacitance transistor with a diffusion blocking layer

A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Negative capacitance transistor with external ferroelectric structure

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

High performance MOSFETs having varying channel structures

A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure is disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.

Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile

High performance MOSFETs having different device characteristics

Method of forming high performance MOSFETs having varying channel structures

Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

Negative capacitance finFET and method of fabricating thereof

A portable electronic device and an image capturing module thereof are disclosed. The image capturing module includes a circuit substrate, a structure reinforcing frame, a plurality of image sensing chips, an adhesive body, and a plurality of lens modules. The circuit substrate has a plurality of first passing openings. The structure reinforcing frame is disposed on the circuit substrate, and the structure reinforcing frame has a plurality of second passing openings respectively communicated with the first passing openings. The image sensing chips are disposed on the circuit substrate and electrically connected with the circuit substrate, and the image sensing chips are coplanarly disposed on a datum plane. The adhesive body is connected between each image sensing chip and the structure reinforcing frame. The lens modules are disposed on the circuit substrate, and the lens modules respectively correspond to the image sensing chips.

Portable electronic device and image capturing module thereof

A portable electronic device and an image capturing module thereof are disclosed. The image capturing module includes a circuit substrate, a structure reinforcing frame, a plurality of image sensing chips, an adhesive body, and a plurality of lens modules. The circuit substrate has a plurality of first passing openings. The structure reinforcing frame is disposed on the circuit substrate, and the structure reinforcing frame has a plurality of second passing openings respectively communicated with the first passing openings. The image sensing chips is electrically connected with the circuit substrate by wire bonding, and the image sensing chips are coplanarly disposed on a datum plane. The adhesive body is connected between each image sensing chip and the structure reinforcing frame. The lens modules are disposed on the circuit substrate, and the lens modules respectively correspond to the image sensing chips.

An image sensing module includes an image sensing unit, a light transmitting unit, a substrate unit and lens unit. The image sensing unit includes an image sensing element having an image sensing area on the top side of the image sensing element. The light transmitting unit includes a light transmitting element supported above the image sensing element by a plurality of support members. The substrate unit includes a flexible substrate disposed on the image sensing element and electrically connected to the image sensing element through a plurality of electrical conductors, and the flexible substrate has at least one through opening for receiving the light transmitting element. The lens unit includes an opaque holder disposed on the flexible substrate to cover the light transmitting element and a lens assembly connected to the opaque holder and disposed above the light transmitting element.

Image sensing module and method of manufacturing the same

A sensor package structure includes a sensing die, a light-filtering sheet, and an annular pressure-sensitive adhesive sheet. An active surface of the sensing die has a sensing region and a connecting region around the sensing region. The periphery contour of sensing die is greater than or equal to the periphery contour of light-filtering sheet. The pressure-sensitive adhesive sheet has two opposite adhesive surfaces and defines an opening. The adhesive surfaces respectively adhere to the connecting region of the sensing die and the inner surface of the light-filtering sheet, and the sensing region faces the inner surface of the light-filtering sheet via the opening. The sensing region is sealed by the pressure-sensitive adhesive sheet and the light-filtering sheet. Thus, the instant disclosure provides the sensor package structure with low cost, high capacity, and high yield. Moreover, the instant disclosure provides a production apparatus for manufacturing the sensor package structure.

Growing community of inventors

New Taipei, Taiwan

Chi-Hsing Hsu