Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Chi-Hsi Wu

Chen-Hua Douglas Yu

Der-Chyang Yeh

Hsien-Wei Chen

An-Jhih Su

Shang-Yun Hou

Wei-Cheng Wu

Kuo-Chiang Ting

Cheng-Hsien Hsieh

Li-Han Hsu

Shin-Puu Jeng

Wei-Yu Chen

Li-Hsien Huang

Hsien-Pin Hu

Ming Shih Yeh

Wen-Hsin Wei

Jing-Cheng Lin

Wensen Hung

Szu-Wei Lu

Tu-Hao Yu

Ying-Ching Shih

Tsung-Shu Lin

Ying-Ju Chen

Hsing-Kuo Hsia

Sung-Hui Huang

Hsiang-Fan Lee

Wen-Chih Chiou

Kim Hong Chen

Szu-Po Huang

Shih-Peng Tai

Po-Hao Tsai

Weiming Chris Chen

Chia-Hao Hsu

Joanna Chaw Yane Yin

Kuang-Hsin Chen

Kuan-Yu Huang

Ting-Yu Yeh

Jie Chen

Tsang-Jiuh Wu

Tsung-Yu Chen

Chin-Chuan Chang

Ming-Shih Yeh

Tien-Chung Yang

Pin-Tso Lin

Wei-Ming Chen

Ta-Wei Liu

Kao-Ting Lai

Tzu-Shiun Sheu

Chia-Hsin Chen

Hung-Jui Kuo

Chih-Wei Wu

Chin-Fu Kao

Li-Chung Kuo

Hua-Wei Tseng

Shih-Chang Ku

Hung-Chi Li

Hou-Ju Li

Heh-Chang Huang

Wei-yu Chen

Yushun Lin

Chih-Chieh Hung

Cheng-Chieh Hsieh

Shu-Yuan Ku

Shiang-Bau Wang

Pu Wang

Sao-Ling Chiu

Ming-Jie Huang

Shih Ting Lin

Shih-Wen Huang

Ping-Kang Huang

Shih-Ting Lin

Chun Hua Chang

Tang-Jung Chiu

Tsung-Yang Hsieh

Chen Kuang-Hsin

Chih-Ching Lin

Shang Y Hou

Chun-Che Chen

Chien-Fu Tseng

Chih-Ta Shen

Jhih-Ming Lin

Ta-Wei Kao

Chung-Te Lin

Ming-Chih Yew

Chun-Sheng Liang

Shi-Tron Lin

Da-Wen Lin

Yuan-Ching Peng

Cheng-Hung Chang

Hsien-Hsin Lin

Yi-Jen Lai

Hsien-Ju Tsou

Chau-Neng Wu

Tan-Chen Lee

Cheng-Chieh Li

Hung-Jui Kou

Kuan-Chung Lu

Hsiang-fan Lee

Di-Houng Lee

Chun-Yi Liu

A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

Integrated circuit package and method

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Encapsulated package including device dies connected via interconnect die

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The first electronic component is between the second and the third electronic components. The first interconnection structures are between the first and the second electronic components. Each first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component, and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between the second and the third electronic components, and electrically connected to the second and the third electronic components. A height of each second interconnection structure is different from a height of each first interconnection structure.

Semiconductor device

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Optical transceiver and manufacturing method thereof

A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Photonic semiconductor device and method of manufacture

A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Semiconductor device with electromagnetic interference film and method of manufacture

Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Via for component electrode connection

A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Package structure and manufacturing method thereof

A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.

Semiconductor device and method for manufacturing the same

A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

Package structure and method of fabricating the same

In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

Method of fabricating a FinFET device

A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Fan-out structure and method of fabricating the same

Growing community of inventors

Hsinchu, Taiwan

Chi-Hsi Wu