Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-How Wu

Horng-Wen Chen

Hung-Wen Chen

Yei-Ren Chen

Zhi-Yong Chang

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CFgas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

In-situ strip process for polysilicon etching in deep sub-micron technology

A method for in-situ reduction of volatile residual contamination on a semiconductor process wafer following a plasma etching process including providing an ambient controlled chamber for accepting transfer of a semiconductor process wafer under controlled ambient conditions following a plasma etching process; providing a heat exchange surface disposed with the ambient controlled chamber in heat exchange relationship with means for heating the heat exchange surface; transferring a semiconductor process wafer having volatile residual contamination under controlled ambient conditions to the ambient controlled chamber; mounting the semiconductor process wafer in heat exchange relationship with the heat exchange surface; and, heating in-situ the heat exchange surface for a time period to thereby heat the semiconductor process wafer to vaporize the volatile residual contamination on the semiconductor process wafer while simultaneously removing a resulting vapor from the ambient controlled chamber.

Method for reducing a low volatility byproduct from a wafer surface following an etching process

A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF,gas. Fifth, the polysilicon layer is etched where exposed by the hard mask. After the polysilicon layer is so patterned in the dry plasma etch chamber, the hard mask layer is stripped away to complete the patterning of the polysilicon layer in the manufacture of the integrated circuit device.

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Tainan, Taiwan

Chi-How Wu