Taiwan Semiconductor Manufacturing Comp. Ltd.

D-link Corporation

Chi-Hao Chang

Tze-Liang Lee

Yu-Lien Huang

Jr-Hung Li

Bor Chiuan Hsieh

Yu-Wen Cho

A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

Gate structures in transistor devices and methods of forming same

A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a recess between the gate spacers, performing a first non-conformal deposition process to fill the recess with a first gate cap material, and planarizing the first gate cap material to remove a portion of the first gate cap material outside the recess.

Semiconductor device and method of forming the same

A method for calibrating a propagation delay in a network trunk includes the step of calculating a time period Ti in a first network switch between sending a marker and receiving a trunk package acknowledgement marker from the second network switch, and a time period Tt in the second switch between receiving the trunk package and the marker and transmitting an acknowledgement marker containing the trunk package back to the first switch, the second switch appending the time period Tt to the acknowledgement marker before sending it back to the first switch. The time gap is read and a time delay caused by sending the trunk package on each channel is calculated. The second switch decodes the received trunk package and calibrates the propagation delay based on the time delay to determine a time gap between the packages in the same channel.

Growing community of inventors

Hsinchu, Taiwan

Chi-Hao Chang